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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-12-01 12:04:24 -0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-12-10 10:24:16 +0100 |
| commit | 988d6ee8b2e8694830036821933372b22f3d1935 (patch) | |
| tree | 05f6a291af464d673c23726ace4bd9ba3353d279 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | d4b1931c149e1cf78a930d7abde00bd378272e6e (diff) | |
| download | lwn-988d6ee8b2e8694830036821933372b22f3d1935.tar.gz lwn-988d6ee8b2e8694830036821933372b22f3d1935.zip | |
drm/i915: add support for mPHY destination on intel_sbi_{read, write}
This way we should be able to write mPHY registers using the Sideband
Interface in the next commit. Also fixed some syntax oddities in the
related code.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 97fbd9d1823b..0760425c892e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4534,6 +4534,10 @@ #define SBI_ADDR 0xC6000 #define SBI_DATA 0xC6004 #define SBI_CTL_STAT 0xC6008 +#define SBI_CTL_DEST_ICLK (0x0<<16) +#define SBI_CTL_DEST_MPHY (0x1<<16) +#define SBI_CTL_OP_IORD (0x2<<8) +#define SBI_CTL_OP_IOWR (0x3<<8) #define SBI_CTL_OP_CRRD (0x6<<8) #define SBI_CTL_OP_CRWR (0x7<<8) #define SBI_RESPONSE_FAIL (0x1<<1) |