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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-11-21 21:54:25 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-12-03 09:29:36 +0100 |
| commit | 73bbf6bd907906dcbdc78f3af38a722c0fe498d8 (patch) | |
| tree | e212bcbf12131ac43b021095701135ad0e2320ec /drivers/gpu/drm/i915/i915_reg.h | |
| parent | aaecdf611a05cac26a94713bad25297e60225c29 (diff) | |
| download | lwn-73bbf6bd907906dcbdc78f3af38a722c0fe498d8.tar.gz lwn-73bbf6bd907906dcbdc78f3af38a722c0fe498d8.zip | |
drm/i915: Fix gen4 GPU reset
On pre-ctg the reset bit directly controls the reset signal. We must
assert it for >=20usec and then deassert it. Bit 1 is a RO status bit
which should also go down when the reset is no longer asserted.
Tested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3102907a96a7..ff1e36f669a2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -83,6 +83,7 @@ #define GRDOM_RENDER (1<<2) #define GRDOM_MEDIA (3<<2) #define GRDOM_MASK (3<<2) +#define GRDOM_RESET_STATUS (1<<1) #define GRDOM_RESET_ENABLE (1<<0) #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ |