diff options
| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2013-09-10 19:36:37 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-09-19 14:11:47 +0200 |
| commit | 515b239269fb67fd167676d335a56ef0c13e53d5 (patch) | |
| tree | bc2e9cf84eb57ab612b95f91e7d8ea1c7676bacc /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 507c1a454809da54af21091875f883e0364c5378 (diff) | |
| download | lwn-515b239269fb67fd167676d335a56ef0c13e53d5.tar.gz lwn-515b239269fb67fd167676d335a56ef0c13e53d5.zip | |
drm/i915: write D_COMP using the mailbox
You can't write it using the MCHBAR mirror, the write will just get
dropped.
This should make us BSpec-compliant, but there's no real bug I could
reproduce that is fixed by this patch.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Fix spelling mistake in the comment that Damien spotted.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 384adfba3983..af6f93ca7296 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1441,6 +1441,8 @@ * device 0 function 0's pci config register 0x44 or 0x48 and matches it in * every way. It is not accessible from the CP register read instructions. * + * Starting from Haswell, you can't write registers using the MCHBAR mirror, + * just read. */ #define MCHBAR_MIRROR_BASE 0x10000 @@ -4724,6 +4726,8 @@ #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 #define GEN6_PCODE_READ_RC6VIDS 0x5 +#define GEN6_PCODE_READ_D_COMP 0x10 +#define GEN6_PCODE_WRITE_D_COMP 0x11 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) #define GEN6_PCODE_DATA 0x138128 |