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authorVille Syrjälä <ville.syrjala@linux.intel.com>2014-02-27 21:59:02 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-03-05 21:30:33 +0100
commit4f1ca9e94057de098d65bc7477e8f89dd51609aa (patch)
tree96b264505b41134772a8f396ac2080eb45b77c70 /drivers/gpu/drm/i915/i915_reg.h
parent295e8bb73a4785b65db6655fbf6ad57c4177b551 (diff)
downloadlwn-4f1ca9e94057de098d65bc7477e8f89dd51609aa.tar.gz
lwn-4f1ca9e94057de098d65bc7477e8f89dd51609aa.zip
drm/i915: Implement WaDisableSDEUnitClockGating:bdw
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d11a9ea5884d..c913ca5c3b39 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4906,6 +4906,9 @@
#define GEN7_UCGCTL4 0x940c
#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
+#define GEN8_UCGCTL6 0x9430
+#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
+
#define GEN6_RPNSWREQ 0xA008
#define GEN6_TURBO_DISABLE (1<<31)
#define GEN6_FREQUENCY(x) ((x)<<25)