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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-11-07 11:05:46 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-11-08 18:10:13 +0100 |
| commit | 38d83c96a3f67ba2cfb7454f310791a3c58e71ad (patch) | |
| tree | 446e13738c1949e6a113a9288ec447213f59c3df /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 7167d7c677ef066c56df276dc35b044c4840151a (diff) | |
| download | lwn-38d83c96a3f67ba2cfb7454f310791a3c58e71ad.tar.gz lwn-38d83c96a3f67ba2cfb7454f310791a3c58e71ad.zip | |
drm/i915: Wire up cpu fifo underrun reporting support for bdw
HW engineers have listened and given us again a real interrupt with
masking and status regs. Yay!
For consistency with other platforms call the #define FIFO_UNDERRUN.
Eventually we also might need to have some enable/disable functions
for bdw display interrupts, but for now open-coding seems to be good
enough.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fe8cb4cc0296..40fe67b539d4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4053,7 +4053,7 @@ #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe))) #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe))) #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe))) -#define GEN8_PIPE_UNDERRUN (1 << 31) +#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) #define GEN8_PIPE_CURSOR_FAULT (1 << 10) |