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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-05-14 17:12:51 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-05-20 17:52:35 +0200 |
| commit | 2da8af54059bd8c0d7bdf1f56b39cbec7f9c6f05 (patch) | |
| tree | 1e5d38013cc33739788576eb27ddde114c5557be /drivers/gpu/drm/i915/i915_reg.h | |
| parent | ed517fbbbd3a01692a667ac18b4a413695513428 (diff) | |
| download | lwn-2da8af54059bd8c0d7bdf1f56b39cbec7f9c6f05.tar.gz lwn-2da8af54059bd8c0d7bdf1f56b39cbec7f9c6f05.zip | |
drm/i915: implement hsw_write_infoframe
Both the control and data registers are completely different now.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fb76b19e32b2..2d49b9507ed0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1697,6 +1697,7 @@ /* Video Data Island Packet control */ #define VIDEO_DIP_DATA 0x61178 #define VIDEO_DIP_CTL 0x61170 +/* Pre HSW: */ #define VIDEO_DIP_ENABLE (1 << 31) #define VIDEO_DIP_PORT_B (1 << 29) #define VIDEO_DIP_PORT_C (2 << 29) @@ -1713,6 +1714,9 @@ #define VIDEO_DIP_FREQ_VSYNC (1 << 16) #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) #define VIDEO_DIP_FREQ_MASK (3 << 16) +/* HSW and later: */ +#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) +#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) /* Panel power sequencing */ #define PP_STATUS 0x61200 |