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| author | Vijay Purushothaman <vijay.a.purushothaman@intel.com> | 2012-09-27 19:13:06 +0530 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-09-28 17:02:08 +0200 |
| commit | 2a8f64ca23447248efaf87c5c7c2cb0c5c3f27e8 (patch) | |
| tree | 6a0050828820fb80994bfbcba81ae388534257ca /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 74a4dd2e4594804ffeb04b3e60ff4cfbf6b8ce10 (diff) | |
| download | lwn-2a8f64ca23447248efaf87c5c7c2cb0c5c3f27e8.tar.gz lwn-2a8f64ca23447248efaf87c5c7c2cb0c5c3f27e8.zip | |
drm/i915: Enable DisplayPort in Valleyview
In valleyview voltageswing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric.
Cleaned up DPLL calculations for Valleyview to support multi display
configurations.
v2: Based on Daniel's feedbacak, moved crt hotplug detect work around as separate
patch. Also moved i9xx_update_pll_dividers to i8xx_update_pll and
i9xx_update_pll.
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: drop spurious whitespace changes.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3f75ee6b5b21..0fe4aad8e424 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -385,12 +385,8 @@ #define DPIO_FASTCLK_DISABLE 0x8100 -#define _DPIO_DATA_LANE0 0x0220 -#define _DPIO_DATA_LANE1 0x0420 -#define _DPIO_DATA_LANE2 0x2620 -#define _DPIO_DATA_LANE3 0x2820 -#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2) -#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3) +#define DPIO_DATA_CHANNEL1 0x8220 +#define DPIO_DATA_CHANNEL2 0x8420 /* * Fence registers |