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| author | Brad Volkin <bradley.d.volkin@intel.com> | 2014-02-18 10:15:51 -0800 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-04-01 22:58:11 +0200 |
| commit | 220375aa12c95744cd71d236f7c1ee39d277b6ed (patch) | |
| tree | 9559aaaf19fb08d248aa1aac327021f0bc105275 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 5947de9b46d472f9596f77bb5a1655c0d6c99f7e (diff) | |
| download | lwn-220375aa12c95744cd71d236f7c1ee39d277b6ed.tar.gz lwn-220375aa12c95744cd71d236f7c1ee39d277b6ed.zip | |
drm/i915: Add register whitelist for DRM master
These are used to implement scanline waits in the X server.
v2: Use #defines instead of magic numbers
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6247843914c8..d90171bd14dc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -416,6 +416,12 @@ /* There are the 4 64-bit counter registers, one for each stream output */ #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8) +#define _GEN7_PIPEA_DE_LOAD_SL 0x70068 +#define _GEN7_PIPEB_DE_LOAD_SL 0x71068 +#define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \ + _GEN7_PIPEA_DE_LOAD_SL, \ + _GEN7_PIPEB_DE_LOAD_SL) + /* * Reset registers */ |