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| author | Carlos Santa <carlos.santa@intel.com> | 2016-08-17 12:30:48 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2016-09-07 16:07:08 -0700 |
| commit | b355f10925fdeb186796eaa4f3e64a7db02c3ccf (patch) | |
| tree | 5219eb541f8944d9b6f805b6bec8c7aa5c3cfb9f /drivers/gpu/drm/i915/i915_pci.c | |
| parent | a13233804686886726aeeb084141d9a759c0b859 (diff) | |
| download | lwn-b355f10925fdeb186796eaa4f3e64a7db02c3ccf.tar.gz lwn-b355f10925fdeb186796eaa4f3e64a7db02c3ccf.zip | |
drm/i915: Move HAS_GMBUS_IRQ definition to platform definition
Moving all GPU features to the platform struct definition allows for
- standard place when adding new features from new platforms
- possible to see supported features when dumping struct
definitions
Signed-off-by: Carlos Santa <carlos.santa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_pci.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_pci.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 60cfc7824da8..616de269d41d 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -181,6 +181,7 @@ static const struct intel_device_info intel_pineview_info = { #define GEN5_FEATURES \ .gen = 5, .num_pipes = 2, \ .need_gfx_hws = 1, .has_hotplug = 1, \ + .has_gmbus_irq = 1, \ .ring_mask = RENDER_RING | BSD_RING, \ GEN_DEFAULT_PIPEOFFSETS, \ CURSOR_OFFSETS @@ -202,6 +203,7 @@ static const struct intel_device_info intel_ironlake_m_info = { .has_llc = 1, \ .has_rc6 = 1, \ .has_rc6p = 1, \ + .has_gmbus_irq = 1, \ GEN_DEFAULT_PIPEOFFSETS, \ CURSOR_OFFSETS @@ -222,6 +224,7 @@ static const struct intel_device_info intel_sandybridge_m_info = { .has_llc = 1, \ .has_rc6 = 1, \ .has_rc6p = 1, \ + .has_gmbus_irq = 1, \ GEN_DEFAULT_PIPEOFFSETS, \ IVB_CURSOR_OFFSETS @@ -247,6 +250,7 @@ static const struct intel_device_info intel_ivybridge_q_info = { .has_psr = 1, \ .has_runtime_pm = 1, \ .has_rc6 = 1, \ + .has_gmbus_irq = 1, \ .need_gfx_hws = 1, .has_hotplug = 1, \ .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ .display_mmio_offset = VLV_DISPLAY_BASE, \ @@ -300,6 +304,7 @@ static const struct intel_device_info intel_cherryview_info = { .has_runtime_pm = 1, .has_resource_streamer = 1, .has_rc6 = 1, + .has_gmbus_irq = 1, .display_mmio_offset = VLV_DISPLAY_BASE, GEN_CHV_PIPEOFFSETS, CURSOR_OFFSETS, @@ -336,6 +341,7 @@ static const struct intel_device_info intel_broxton_info = { .has_resource_streamer = 1, .has_rc6 = 1, .has_dp_mst = 1, + .has_gmbus_irq = 1, GEN_DEFAULT_PIPEOFFSETS, IVB_CURSOR_OFFSETS, BDW_COLORS, |