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author | Chris Wilson <chris@chris-wilson.co.uk> | 2019-03-14 22:38:37 +0000 |
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committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-03-15 09:04:54 +0000 |
commit | 51d623b675b6624a2b2409fd0c45d1d26c180827 (patch) | |
tree | 685339d9bb91d715d78d814884b960e6bb30266b /drivers/gpu/drm/i915/i915_pci.c | |
parent | cbecbccaa120fd976c2777ea80035675d6e39ec0 (diff) | |
download | lwn-51d623b675b6624a2b2409fd0c45d1d26c180827.tar.gz lwn-51d623b675b6624a2b2409fd0c45d1d26c180827.zip |
drm/i915: Drop address size from ppgtt_type
With the introduction of the separate addressable bits into the device
info, we can remove the conflation of the ppgtt size from the ppgtt
type.
Based on a patch by Bob Paauwe.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190314223839.28258-3-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/i915_pci.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_pci.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index a13ac0f3e528..ef7410c492fd 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -498,7 +498,7 @@ static const struct intel_device_info intel_haswell_gt3_info = { .page_sizes = I915_GTT_PAGE_SIZE_4K | \ I915_GTT_PAGE_SIZE_2M, \ .has_logical_ring_contexts = 1, \ - .ppgtt_type = INTEL_PPGTT_FULL_4LVL, \ + .ppgtt_type = INTEL_PPGTT_FULL, \ .ppgtt_size = 48, \ .has_64bit_reloc = 1, \ .has_reset_engine = 1 @@ -621,7 +621,7 @@ static const struct intel_device_info intel_skylake_gt4_info = { .has_logical_ring_contexts = 1, \ .has_logical_ring_preemption = 1, \ .has_guc = 1, \ - .ppgtt_type = INTEL_PPGTT_FULL_4LVL, \ + .ppgtt_type = INTEL_PPGTT_FULL, \ .ppgtt_size = 48, \ .has_reset_engine = 1, \ .has_snoop = true, \ |