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| author | Armin Reese <armin.c.reese@intel.com> | 2012-03-30 16:20:16 -0700 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-04-17 17:54:51 +0200 |
| commit | 446f254566ea8911c9e19c7bc8a162fc0e53cf31 (patch) | |
| tree | 22c60cf8cf85a7e87676780faeca086dafbb2596 /drivers/gpu/drm/i915/i915_irq.c | |
| parent | 83de97c885b633ab6d12346a406911fadeb85f8c (diff) | |
| download | lwn-446f254566ea8911c9e19c7bc8a162fc0e53cf31.tar.gz lwn-446f254566ea8911c9e19c7bc8a162fc0e53cf31.zip | |
drm/i915: Mask reserved bits in display/sprite address registers
The purpose of this patch is to avoid zeroing the lower 12 reserved bits
of surface base address registers (framebuffer & sprite). There are bits
in that range that may occasionally be set by BIOS or by other components.
Signed-off-by: Armin Reese <armin.c.reese@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 967b92eaf797..ab023ca73b45 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1368,7 +1368,8 @@ static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) obj = work->pending_flip_obj; if (INTEL_INFO(dev)->gen >= 4) { int dspsurf = DSPSURF(intel_crtc->plane); - stall_detected = I915_READ(dspsurf) == obj->gtt_offset; + stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == + obj->gtt_offset; } else { int dspaddr = DSPADDR(intel_crtc->plane); stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + |