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authorChris Wilson <chris@chris-wilson.co.uk>2016-06-30 15:33:45 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2016-06-30 15:42:34 +0100
commit76f8421f2a67cdecd616705b7a0c3750d6d42c05 (patch)
treeef1c0b47412308e20c7e839ffef4e199b95b965a /drivers/gpu/drm/i915/i915_drv.h
parent87273b7110a031c7b258f8c05efcd88194f79fe8 (diff)
downloadlwn-76f8421f2a67cdecd616705b7a0c3750d6d42c05.tar.gz
lwn-76f8421f2a67cdecd616705b7a0c3750d6d42c05.zip
drm/i915: Perform Sandybridge BSD tail write under the forcewake
Since we have a sequence of register reads and writes, we can reduce the latency of starting the BSD ring by performing all the mmio operations under the same forcewake wakeref. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1467297225-21379-62-git-send-email-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 48d30676455e..485ab1148181 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3882,6 +3882,7 @@ __raw_write(64, q)
*/
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
+#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
/* "Broadcast RGB" property */