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authorManasi Navare <manasi.d.navare@intel.com>2018-11-28 12:26:23 -0800
committerManasi Navare <manasi.d.navare@intel.com>2018-11-29 12:31:14 -0800
commita600622c09ddf7da660ca714d5644ecf270426fc (patch)
treee58c920943155996b1c7ed5ae9a1af57c451410d /drivers/gpu/drm/i915/i915_drv.h
parenta311b0b5d2094029dce2369d686044131e19e006 (diff)
downloadlwn-a600622c09ddf7da660ca714d5644ecf270426fc.tar.gz
lwn-a600622c09ddf7da660ca714d5644ecf270426fc.zip
drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
1. Disable Left/right VDSC branch in DSS Ctrl reg depending on the number of VDSC engines being used 2. Disable joiner in DSS Ctrl reg v4: * Remove encoder, make crtc_state const (Ville) v3 (From Manasi): * Add Disable PG2 for VDSC on eDP v2 (From Manasi): * Use old_crtc_state to find dsc params * Add a condition to disable only if dsc state compression is enabled * Use correct DSS CTL regs Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-12-manasi.d.navare@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 06d1eaeeba7a..43ac6873a2bb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3342,6 +3342,7 @@ extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
bool enable);
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);