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| author | Chon Ming Lee <chon.ming.lee@intel.com> | 2014-04-09 13:28:14 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-05-12 19:50:11 +0200 |
| commit | a09cadddde3819dfbb04262f3db12082d4c7b695 (patch) | |
| tree | b8575d9204c1e6d2b447964bc59a36ab5a22a688 /drivers/gpu/drm/i915/i915_drv.h | |
| parent | c294c545f786383d5f9b5e71eaad4a7603c581bc (diff) | |
| download | lwn-a09cadddde3819dfbb04262f3db12082d4c7b695.tar.gz lwn-a09cadddde3819dfbb04262f3db12082d4c7b695.zip | |
drm/i915/chv: Add DPIO offset for Cherryview. v3
CHV has 2 display phys. First phy (IOSF offset 0x1A) has two channels,
and second phy (IOSF offset 0x12) has single channel. The first phy is
used for port B and port C, while second phy is only for port D.
v2: Move the pipe to determine which phy to select for
vlv_dpio_read/vlv_dpio_write to another patch. (Daniel)
v3: Rebase the code based on rework on how to calculate DPIO offset.
Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5efe3222f1e8..edb768a39a40 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -92,7 +92,7 @@ enum port { }; #define port_name(p) ((p) + 'A') -#define I915_NUM_PHYS_VLV 1 +#define I915_NUM_PHYS_VLV 2 enum dpio_channel { DPIO_CH0, |