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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2015-09-14 15:19:59 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-09-23 14:39:18 +0200 |
| commit | 7b24c9a696c1c68eaa471a27bf467e97a9986fa9 (patch) | |
| tree | b71211080b31619a8c95c4c437b641823af8f3f0 /drivers/gpu/drm/i915/i915_drv.h | |
| parent | b8bf5d7fe0dee64ed0a73fa1e95ba8e464d605da (diff) | |
| download | lwn-7b24c9a696c1c68eaa471a27bf467e97a9986fa9.tar.gz lwn-7b24c9a696c1c68eaa471a27bf467e97a9986fa9.zip | |
drm/i915: don't enable FBC when pixel rate exceeds 95% on HSW/BDW
BSpec says we shouldn't enable FBC on HSW/BDW when the pipe pixel rate
exceeds 95% of the core display clock.
v2:
- HSW also needs the WA (Ville).
- Add the WA name (Ville).
- Use the current cdclk (Ville).
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ffd4ab111957..e5242c0ce4f1 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -949,6 +949,7 @@ struct i915_fbc { FBC_ROTATION, /* rotation is not supported */ FBC_IN_DBG_MASTER, /* kernel debugger is active */ FBC_BAD_STRIDE, /* stride is not supported */ + FBC_PIXEL_RATE, /* pixel rate is too big */ } no_fbc_reason; bool (*fbc_enabled)(struct drm_i915_private *dev_priv); |