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| author | Jani Nikula <jani.nikula@intel.com> | 2013-05-22 15:36:16 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-05-23 23:24:03 +0200 |
| commit | 59de08136f0c8d91bfd607d03cf722c5b6c60d1b (patch) | |
| tree | 443e418a7b066d1a5b15db33952744a2f2f4ae85 /drivers/gpu/drm/i915/i915_drv.h | |
| parent | edc3d8848dc9fe2a470316363dab8ef211d77e01 (diff) | |
| download | lwn-59de08136f0c8d91bfd607d03cf722c5b6c60d1b.tar.gz lwn-59de08136f0c8d91bfd607d03cf722c5b6c60d1b.zip | |
drm/i915: group sideband register accessors to a new file
Group both the HSW/LPT SBI interface and VLV IOSF sideband register
accessor functions into a new file. No functional changes.
v2: also move intel_sbi_{read,write} (Daniel)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7772bb6f73ba..5a0dfca88668 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1929,9 +1929,17 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); + +/* intel_sideband.c */ int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val); int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val); +u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg); +void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val); +u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, + enum intel_sbi_destination destination); +void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, + enum intel_sbi_destination destination); int vlv_gpu_freq(int ddr_freq, int val); int vlv_freq_opcode(int ddr_freq, int val); |