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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-03-28 13:39:25 -0700 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-03-28 23:52:31 +0200 |
| commit | 57f350b6722f9569f407872f6ead56e2d221d98a (patch) | |
| tree | e603a42f2af8a94fdfccf9f31b54435b2bdb037a /drivers/gpu/drm/i915/i915_drv.h | |
| parent | 25eb05fc5ac7a432e1a3a723f9af206142cd07fa (diff) | |
| download | lwn-57f350b6722f9569f407872f6ead56e2d221d98a.tar.gz lwn-57f350b6722f9569f407872f6ead56e2d221d98a.zip | |
drm/i915: add DPIO support
ValleyView puts some display related registers like the PLL controls and
dividers behind the DPIO bus. Add simple indirect register access
routines to get to those registers.
v2: move new wait_for macro to intel_drv.h (Ben)
fix DPIO_PKT double write (Ben)
add debugfs file
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 30612f52b93b..32f3731b1a18 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -360,6 +360,10 @@ typedef struct drm_i915_private { /* protects the irq masks */ spinlock_t irq_lock; + + /* DPIO indirect register protection */ + spinlock_t dpio_lock; + /** Cached value of IMR to avoid reads in updating the bitfield */ u32 pipestat[2]; u32 irq_mask; |