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authorAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>2014-10-29 11:32:31 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-11-07 18:41:42 +0100
commit1e6f2ddc88fec990ef4fb1aa3b7cb9941df0321b (patch)
tree473b05b221f28aacf7325485922ecc7e7346b576 /drivers/gpu/drm/i915/i915_drv.h
parent0a88818d093b4d5746d7b3af3acc2b2bddd59808 (diff)
downloadlwn-1e6f2ddc88fec990ef4fb1aa3b7cb9941df0321b.tar.gz
lwn-1e6f2ddc88fec990ef4fb1aa3b7cb9941df0321b.zip
drm/i915: Convert shared dpll reference count to a crtc mask
This will be used in a follow up patch to properly release shared DPLLs without relying on the shared_dpll field in pipe_config. v2: Fix white space error (Ville) Use hweight32() (Ville) Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0e12c6ac2be5..4f4eef701ce0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -230,7 +230,7 @@ struct intel_dpll_hw_state {
};
struct intel_shared_dpll {
- int refcount; /* count of number of CRTCs sharing this PLL */
+ unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
int active; /* count of number of active CRTCs (i.e. DPMS on) */
bool on; /* is the PLL actually active? Disabled during modeset */
const char *name;