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| author | Imre Deak <imre.deak@intel.com> | 2014-06-05 20:31:47 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2014-06-23 10:02:03 +0300 |
| commit | bfafe93a1cd466ef318b7e5f6c65f59aee147791 (patch) | |
| tree | 35ba06381f0cb31c9ed37c0216c98b7e8d739677 /drivers/gpu/drm/i915/i915_drv.h | |
| parent | a497c3ba1d97fc69c1e78e7b96435ba8c2cb42ee (diff) | |
| download | lwn-bfafe93a1cd466ef318b7e5f6c65f59aee147791.tar.gz lwn-bfafe93a1cd466ef318b7e5f6c65f59aee147791.zip | |
drm/i915: cache hw power well enabled state
Jesse noticed that the punit communication needed to query the VLV power
well status can cause substantial delays. Since we can query the state
frequently, for example during I2C transfers, maintain a cached version
of the HW state to get rid of this delay.
This fixes at least one reported regression where boot time increased by
~4 seconds due to frequent power well state queries on VLV during eDP
EDID read.
This regression has been introduced in
commit bb4932c4f17b68f34645ffbcf845e4c29d17290b
Author: Imre Deak <imre.deak@intel.com>
Date: Mon Apr 14 20:24:33 2014 +0300
drm/i915: vlv: check port power domain instead of only D0 for eDP VDD on
Reported-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 49414d30e8d4..a47fbf60b781 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -977,6 +977,8 @@ struct i915_power_well { bool always_on; /* power well enable/disable usage count */ int count; + /* cached hw enabled state */ + bool hw_enabled; unsigned long domains; unsigned long data; const struct i915_power_well_ops *ops; |