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authorYuanhan Liu <yuanhan.liu@linux.intel.com>2010-11-08 17:09:41 +0800
committerChris Wilson <chris@chris-wilson.co.uk>2010-11-08 09:36:48 +0000
commitba4f01a30480cdcd516b782f77a6e0951b83df1c (patch)
treef8e77233ebb4912a918f1e47c411b5208b94964b /drivers/gpu/drm/i915/i915_drv.h
parent67e92af01cb6f7e9a5fd5c930c43cd6f6ef45929 (diff)
downloadlwn-ba4f01a30480cdcd516b782f77a6e0951b83df1c.tar.gz
lwn-ba4f01a30480cdcd516b782f77a6e0951b83df1c.zip
drm/i915: trace down all the register write and read
Add two tracepoints at I915_WRITE/READ for tracing down all the register write and read. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h61
1 files changed, 53 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 621234265454..220ce53d4a9c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -32,6 +32,7 @@
#include "i915_reg.h"
#include "intel_bios.h"
+#include "i915_trace.h"
#include "intel_ringbuffer.h"
#include <linux/io-mapping.h>
#include <linux/i2c.h>
@@ -1173,14 +1174,58 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove
LOCK_TEST_WITH_RETURN(dev, file_priv); \
} while (0)
-#define I915_READ(reg) readl(dev_priv->regs + (reg))
-#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
-#define I915_READ16(reg) readw(dev_priv->regs + (reg))
-#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
-#define I915_READ8(reg) readb(dev_priv->regs + (reg))
-#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
-#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
-#define I915_READ64(reg) readq(dev_priv->regs + (reg))
+static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg, int len)
+{
+ u64 val = 0;
+
+ switch (len) {
+ case 8:
+ val = readq(dev_priv->regs + reg);
+ break;
+ case 4:
+ val = readl(dev_priv->regs + reg);
+ break;
+ case 2:
+ val = readw(dev_priv->regs + reg);
+ break;
+ case 1:
+ val = readb(dev_priv->regs + reg);
+ break;
+ }
+ trace_i915_reg_rw('R', reg, val, len);
+
+ return val;
+}
+
+static inline void
+i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
+{
+ /* Trace down the write operation before the real write */
+ trace_i915_reg_rw('W', reg, val, len);
+ switch (len) {
+ case 8:
+ writeq(val, dev_priv->regs + reg);
+ break;
+ case 4:
+ writel(val, dev_priv->regs + reg);
+ break;
+ case 2:
+ writew(val, dev_priv->regs + reg);
+ break;
+ case 1:
+ writeb(val, dev_priv->regs + reg);
+ break;
+ }
+}
+
+#define I915_READ(reg) i915_read(dev_priv, (reg), 4)
+#define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val), 4)
+#define I915_READ16(reg) i915_read(dev_priv, (reg), 2)
+#define I915_WRITE16(reg, val) i915_write(dev_priv, (reg), (val), 2)
+#define I915_READ8(reg) i915_read(dev_priv, (reg), 1)
+#define I915_WRITE8(reg, val) i915_write(dev_priv, (reg), (val), 1)
+#define I915_WRITE64(reg, val) i915_write(dev_priv, (reg), (val), 8)
+#define I915_READ64(reg) i915_read(dev_priv, (reg), 8)
#define POSTING_READ(reg) (void)I915_READ(reg)
#define POSTING_READ16(reg) (void)I915_READ16(reg)