diff options
| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2014-11-14 08:52:40 -0800 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-12-03 09:35:09 +0100 |
| commit | a6cbdb8e37d65bbf827fc31ee68b50b1e562a8ba (patch) | |
| tree | 8d2cedeec2b39238109d484e680c112d65af06f3 /drivers/gpu/drm/i915/i915_debugfs.c | |
| parent | 995d304774966bf1e3013b5bf7df554b3d807b17 (diff) | |
| download | lwn-a6cbdb8e37d65bbf827fc31ee68b50b1e562a8ba.tar.gz lwn-a6cbdb8e37d65bbf827fc31ee68b50b1e562a8ba.zip | |
drm/i915: VLV/CHV PSR debugfs.
Add debugfs support for Valleyview and Cherryview considering that
we have PSR per pipe and we don't have any kind of
performance counter as we have on other platforms that support PSR.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_debugfs.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_debugfs.c | 34 |
1 files changed, 29 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 779a275eb1fd..eed740252945 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2155,6 +2155,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) struct drm_device *dev = node->minor->dev; struct drm_i915_private *dev_priv = dev->dev_private; u32 psrperf = 0; + u32 stat[3]; + enum pipe pipe; bool enabled = false; intel_runtime_pm_get(dev_priv); @@ -2169,14 +2171,36 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) seq_printf(m, "Re-enable work scheduled: %s\n", yesno(work_busy(&dev_priv->psr.work.work))); - enabled = HAS_PSR(dev) && - I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; - seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled)); + if (HAS_PSR(dev)) { + if (HAS_DDI(dev)) + enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; + else { + for_each_pipe(dev_priv, pipe) { + stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & + VLV_EDP_PSR_CURR_STATE_MASK; + if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || + (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) + enabled = true; + } + } + } + seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); - if (HAS_PSR(dev)) + if (!HAS_DDI(dev)) + for_each_pipe(dev_priv, pipe) { + if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || + (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) + seq_printf(m, " pipe %c", pipe_name(pipe)); + } + seq_puts(m, "\n"); + + /* CHV PSR has no kind of performance counter */ + if (HAS_PSR(dev) && HAS_DDI(dev)) { psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & EDP_PSR_PERF_CNT_MASK; - seq_printf(m, "Performance_Counter: %u\n", psrperf); + + seq_printf(m, "Performance_Counter: %u\n", psrperf); + } mutex_unlock(&dev_priv->psr.lock); intel_runtime_pm_put(dev_priv); |