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authorRodrigo Vivi <rodrigo.vivi@intel.com>2015-11-23 14:16:40 -0800
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-11-24 13:33:10 +0100
commit05eec3c2709d8966cbfcc7cd395f37889c492678 (patch)
treedc1850ef36a1809d183cea6f82b231d09bec7501 /drivers/gpu/drm/i915/i915_debugfs.c
parentbb929cbc1f58c72eaf7981281dbb024ad92ef24d (diff)
downloadlwn-05eec3c2709d8966cbfcc7cd395f37889c492678.tar.gz
lwn-05eec3c2709d8966cbfcc7cd395f37889c492678.zip
drm/i915: Remove PSR Perf Counter for SKL+
Whenever DMC firmware put the HW into DC State a bunch of registers including this perf counter is reset to 0. Even with PSR active and working we could still read "Performance_Counter: 0" what will misslead people to believe PSR is broken. For instance on SKL we can only see PC10 residency with screen on if PSR is working properly. However Performance_Counter was showing 0. Even if it restored properly on DC6 exit we don't want to give users the wrong impression that PSR is not working while we know for sure it is. So, it is better to remove this counter information while we don't have a better way to track PSR residency. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Durgadoss R <durgadoss.r@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_debugfs.c')
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b28da6fd7540..a728ff11e389 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2582,8 +2582,11 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
}
seq_puts(m, "\n");
- /* CHV PSR has no kind of performance counter */
- if (HAS_DDI(dev)) {
+ /*
+ * VLV/CHV PSR has no kind of performance counter
+ * SKL+ Perf counter is reset to 0 everytime DC state is entered
+ */
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
psrperf = I915_READ(EDP_PSR_PERF_CNT) &
EDP_PSR_PERF_CNT_MASK;