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| author | Jarkko Nikula <jarkko.nikula@linux.intel.com> | 2017-05-30 17:31:21 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2017-06-06 20:01:15 +0100 |
| commit | fc0b2acc754a183aa79e2abb8bca8fd915832694 (patch) | |
| tree | 9c9292e44d473ed9168d0d4b023b4fbcd08bc4bd /drivers/gpu/drm/drm_atomic_helper.c | |
| parent | 2ea659a9ef488125eb46da6eb571de5eae5c43f6 (diff) | |
| download | lwn-fc0b2acc754a183aa79e2abb8bca8fd915832694.tar.gz lwn-fc0b2acc754a183aa79e2abb8bca8fd915832694.zip | |
spi: pxa2xx: Add support for Intel Cannonlake
Intel Cannonlake LPSS SPI has up to four chip selects per port like in
Broxton and is clocked like Sunrisepoint and Kaby Lake. Add a new type
LPSS_CNL_SSP and configuration that enable runtime chip select detection
and use the same FIFO thresholds than in Sunrisepoint.
Patch adds support for both Cannonlake SoC and PCH.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/gpu/drm/drm_atomic_helper.c')
0 files changed, 0 insertions, 0 deletions