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| author | Andrzej Hajda <a.hajda@samsung.com> | 2017-02-01 08:47:48 +0100 |
|---|---|---|
| committer | Archit Taneja <architt@codeaurora.org> | 2017-02-02 15:15:29 +0530 |
| commit | 269ed8eec9c2e66a00e4c127e4c06bf87d518112 (patch) | |
| tree | 50ba7870b304b82b7a66261a64ce962822dd5efe /drivers/gpu/drm/bridge/sil-sii8620.h | |
| parent | bf1722cab55a32a7a18c0155034351084bac59fa (diff) | |
| download | lwn-269ed8eec9c2e66a00e4c127e4c06bf87d518112.tar.gz lwn-269ed8eec9c2e66a00e4c127e4c06bf87d518112.zip | |
drm/bridge/sii8620: send EMSC features on request
Device should report to the peer which features are really supported.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1485935272-17337-22-git-send-email-a.hajda@samsung.com
Diffstat (limited to 'drivers/gpu/drm/bridge/sil-sii8620.h')
| -rw-r--r-- | drivers/gpu/drm/bridge/sil-sii8620.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/bridge/sil-sii8620.h b/drivers/gpu/drm/bridge/sil-sii8620.h index 613943aaf90d..312b07f38a09 100644 --- a/drivers/gpu/drm/bridge/sil-sii8620.h +++ b/drivers/gpu/drm/bridge/sil-sii8620.h @@ -1298,14 +1298,14 @@ /* MDT Transmit Control, default value: 0x70 */ #define REG_MDT_XMIT_CTRL 0x0588 -#define BIT_MDT_XMIT_CTRL_MDT_XMIT_EN BIT(7) -#define BIT_MDT_XMIT_CTRL_MDT_XMIT_CMD_MERGE_EN BIT(6) -#define BIT_MDT_XMIT_CTRL_MDT_XMIT_FIXED_BURST_LEN BIT(5) -#define BIT_MDT_XMIT_CTRL_MDT_XMIT_FIXED_AID BIT(4) -#define BIT_MDT_XMIT_CTRL_MDT_XMIT_SINGLE_RUN_EN BIT(3) -#define BIT_MDT_XMIT_CTRL_MDT_CLR_ABORT_WAIT BIT(2) -#define BIT_MDT_XMIT_CTRL_MDT_XFIFO_CLR_ALL BIT(1) -#define BIT_MDT_XMIT_CTRL_MDT_XFIFO_CLR_CUR BIT(0) +#define BIT_MDT_XMIT_CTRL_EN BIT(7) +#define BIT_MDT_XMIT_CTRL_CMD_MERGE_EN BIT(6) +#define BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN BIT(5) +#define BIT_MDT_XMIT_CTRL_FIXED_AID BIT(4) +#define BIT_MDT_XMIT_CTRL_SINGLE_RUN_EN BIT(3) +#define BIT_MDT_XMIT_CTRL_CLR_ABORT_WAIT BIT(2) +#define BIT_MDT_XMIT_CTRL_XFIFO_CLR_ALL BIT(1) +#define BIT_MDT_XMIT_CTRL_XFIFO_CLR_CUR BIT(0) /* MDT Receive WRITE Port, default value: 0x00 */ #define REG_MDT_XMIT_WRITE_PORT 0x0589 |