diff options
| author | Liu Ying <victor.liu@nxp.com> | 2022-07-01 14:56:32 +0800 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2022-07-04 16:17:05 +0200 |
| commit | 591129d3db266648823bb953ebbc28c92e059bf3 (patch) | |
| tree | 887ed5f1551c5a33041aded127a20fa6ba5f7b6c /drivers/gpu/drm/bridge/fsl-ldb.c | |
| parent | bf43e4521ff3223a613f3a496991a22a4d78e04b (diff) | |
| download | lwn-591129d3db266648823bb953ebbc28c92e059bf3.tar.gz lwn-591129d3db266648823bb953ebbc28c92e059bf3.zip | |
drm/bridge: fsl-ldb: Fix mode clock rate validation
With LVDS dual link, up to 160MHz mode clock rate is supported.
With LVDS single link, up to 80MHz mode clock rate is supported.
Fix mode clock rate validation by swapping the maximum mode clock
rates of the two link modes.
Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge")
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Robert Foss <robert.foss@linaro.org>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220701065634.4027537-2-victor.liu@nxp.com
Diffstat (limited to 'drivers/gpu/drm/bridge/fsl-ldb.c')
| -rw-r--r-- | drivers/gpu/drm/bridge/fsl-ldb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c index b2675c769a55..3cb3b310e283 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -233,7 +233,7 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge, { struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); - if (mode->clock > (fsl_ldb->lvds_dual_link ? 80000 : 160000)) + if (mode->clock > (fsl_ldb->lvds_dual_link ? 160000 : 80000)) return MODE_CLOCK_HIGH; return MODE_OK; |