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| author | Jonathan Kim <jonathan.kim@amd.com> | 2022-08-26 22:04:15 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-06-09 12:35:43 -0400 |
| commit | a9818854ea7870ec5464d37b72c89f5fc198708e (patch) | |
| tree | 87d6f28be3c27524c2992b0b01774e5149a499a4 /drivers/gpu/drm/amd/include | |
| parent | 0de4ec9a03537bd2b189b5afbf83acd6b72b0258 (diff) | |
| download | lwn-a9818854ea7870ec5464d37b72c89f5fc198708e.tar.gz lwn-a9818854ea7870ec5464d37b72c89f5fc198708e.zip | |
drm/amdgpu: expose debug api for mes
Similar to the F32 HWS, the RS64 HWS for GFX11 now supports a multi-process
debug API.
The skip_process_ctx_clear ADD_QUEUE requirement is to prevent the MES
from clearing the process context when the first queue is added to the
scheduler in order to maintain debug mode settings during queue preemption
and restore. The MES clears the process context in this case due to an
unresolved FW caching bug during normal mode operations.
During debug mode, the KFD will hold a reference to the target process
so the process context should never go stale and MES can afford to skip
this requirement.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/mes_v11_api_def.h | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/include/mes_v11_api_def.h b/drivers/gpu/drm/amd/include/mes_v11_api_def.h index dc694cb246d9..f3c15f18ddb5 100644 --- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h +++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h @@ -274,7 +274,8 @@ union MESAPI__ADD_QUEUE { uint32_t is_kfd_process : 1; uint32_t trap_en : 1; uint32_t is_aql_queue : 1; - uint32_t reserved : 20; + uint32_t skip_process_ctx_clear : 1; + uint32_t reserved : 19; }; struct MES_API_STATUS api_status; uint64_t tma_addr; @@ -523,6 +524,7 @@ enum MESAPI_MISC_OPCODE { MESAPI_MISC__QUERY_STATUS, MESAPI_MISC__READ_REG, MESAPI_MISC__WAIT_REG_MEM, + MESAPI_MISC__SET_SHADER_DEBUGGER, MESAPI_MISC__MAX, }; @@ -561,6 +563,20 @@ struct QUERY_STATUS { uint32_t context_id; }; +struct SET_SHADER_DEBUGGER { + uint64_t process_context_addr; + union { + struct { + uint32_t single_memop : 1; /* SQ_DEBUG.single_memop */ + uint32_t single_alu_op : 1; /* SQ_DEBUG.single_alu_op */ + uint32_t reserved : 30; + }; + uint32_t u32all; + } flags; + uint32_t spi_gdbg_per_vmid_cntl; + uint32_t tcp_watch_cntl[4]; /* TCP_WATCHx_CNTL */ +}; + union MESAPI__MISC { struct { union MES_API_HEADER header; @@ -573,6 +589,9 @@ union MESAPI__MISC { struct QUERY_STATUS query_status; struct READ_REG read_reg; struct WAIT_REG_MEM wait_reg_mem; + struct SET_SHADER_DEBUGGER set_shader_debugger; + enum MES_AMD_PRIORITY_LEVEL queue_sch_level; + uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS]; }; }; |