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| author | Alex Deucher <alexander.deucher@amd.com> | 2019-05-15 13:53:14 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-05-24 12:21:00 -0500 |
| commit | e74609cb425371cf6a5baba0a76073b3be34625f (patch) | |
| tree | 6188b1882f5c7865ba60ef8dacb8c579a699a681 /drivers/gpu/drm/amd/amdgpu/soc15.c | |
| parent | 0cd8afaef19927803b7bb0808e09d59a3e405505 (diff) | |
| download | lwn-e74609cb425371cf6a5baba0a76073b3be34625f.tar.gz lwn-e74609cb425371cf6a5baba0a76073b3be34625f.zip | |
drm/amdgpu/vega20: use mode1 reset for RAS and XGMI
If RAS or XGMI are enabled, you have to use mode1 reset rather
than BACO.
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index f9c9cacc5c50..32dc5a128249 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -65,6 +65,8 @@ #include "dce_virtual.h" #include "mxgpu_ai.h" #include "amdgpu_smu.h" +#include "amdgpu_ras.h" +#include "amdgpu_xgmi.h" #include <uapi/linux/kfd_ioctl.h> #define mmMP0_MISC_CGTT_CTRL0 0x01b9 @@ -485,6 +487,13 @@ static int soc15_asic_reset(struct amdgpu_device *adev) soc15_asic_get_baco_capability(adev, &baco_reset); else baco_reset = false; + if (baco_reset) { + struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0); + struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); + + if (hive || (ras && ras->supported)) + baco_reset = false; + } break; default: baco_reset = false; |