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| author | Likun Gao <Likun.Gao@amd.com> | 2018-07-10 20:22:36 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-09-14 09:34:57 -0500 |
| commit | ad5a67a7ea87e625721a5d0c4e9f12100372f1f6 (patch) | |
| tree | 35f6751b275743c988922e33941b88f2301bd1bf /drivers/gpu/drm/amd/amdgpu/soc15.c | |
| parent | be9699e3923000ea32c2f4522e1e4de333d21d47 (diff) | |
| download | lwn-ad5a67a7ea87e625721a5d0c4e9f12100372f1f6.tar.gz lwn-ad5a67a7ea87e625721a5d0c4e9f12100372f1f6.zip | |
drm/amdgpu: add soc15 support for picasso
Add the IP blocks, clock and powergating flags, and common clockgating support.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index fc0cb7d38c9f..d3b73afcb871 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -486,6 +486,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) case CHIP_VEGA10: case CHIP_VEGA12: case CHIP_RAVEN: + case CHIP_PICASSO: vega10_reg_base_init(adev); break; case CHIP_VEGA20: @@ -724,6 +725,25 @@ static int soc15_common_early_init(void *handle) adev->external_rev_id = 0x1; break; + case CHIP_PICASSO: + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_GFX_CP_LS | + AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGLS | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_BIF_LS | + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_ROM_MGCG | + AMD_CG_SUPPORT_MC_MGCG | + AMD_CG_SUPPORT_MC_LS | + AMD_CG_SUPPORT_SDMA_MGCG | + AMD_CG_SUPPORT_SDMA_LS; + + adev->pg_flags = 0; + + adev->external_rev_id = adev->rev_id + 0x41; + break; default: /* FIXME: not supported yet */ return -EINVAL; @@ -924,6 +944,7 @@ static int soc15_common_set_clockgating_state(void *handle, state == AMD_CG_STATE_GATE ? true : false); break; case CHIP_RAVEN: + case CHIP_PICASSO: adev->nbio_funcs->update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE ? true : false); adev->nbio_funcs->update_medium_grain_light_sleep(adev, |