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| author | Le Ma <le.ma@amd.com> | 2020-09-05 22:53:24 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-10 00:01:34 -0500 |
| commit | 42b72608ae228e8a27bb601d7344004e37bf5e7b (patch) | |
| tree | 26ed7a559e13b1bc64f89eac163e3d5a76b1ca93 /drivers/gpu/drm/amd/amdgpu/soc15.c | |
| parent | dd9dd42528308f0534d2be261ba062f948af70c8 (diff) | |
| download | lwn-42b72608ae228e8a27bb601d7344004e37bf5e7b.tar.gz lwn-42b72608ae228e8a27bb601d7344004e37bf5e7b.zip | |
drm/amdgpu: add register base init for aldebaran (v2)
v1: add aldebaran_reg_base_init function to initialize
register base for aldebaran (Le)
v2: update VCN HWIP and initialize base offset (James)
Signed-off-by: Le Ma <le.ma@amd.com>
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 230caaa3513f..a75e1505b47d 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -891,6 +891,9 @@ static void soc15_reg_base_init(struct amdgpu_device *adev) case CHIP_ARCTURUS: arct_reg_base_init(adev); break; + case CHIP_ALDEBARAN: + aldebaran_reg_base_init(adev); + break; default: DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); break; |