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author | Rex Zhu <rex.zhu@amd.com> | 2018-07-05 16:34:13 +0800 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2018-07-10 14:16:39 -0500 |
commit | 73b1917454b3639ac1926c869f51e0dc20a0d22f (patch) | |
tree | f17d07fe289e897ad5245eb6a80252841cb3803c /drivers/gpu/drm/amd/amdgpu/amdgpu.h | |
parent | 02374bbd3bfa38cc6922fe56736716308c48f538 (diff) | |
download | lwn-73b1917454b3639ac1926c869f51e0dc20a0d22f.tar.gz lwn-73b1917454b3639ac1926c869f51e0dc20a0d22f.zip |
drm/amdgpu: Add CLK IP base offset
so we can read/write the registers in CLK domain
through RREG32/WREG32_SOC15
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 8a440b9fa0fd..b38c170fb95c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1398,6 +1398,7 @@ enum amd_hw_ip_block_type { PWR_HWIP, NBIF_HWIP, THM_HWIP, + CLK_HWIP, MAX_HWIP }; |