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authorPatrice Chotard <patrice.chotard@st.com>2016-08-10 09:39:11 +0200
committerLee Jones <lee.jones@linaro.org>2016-08-10 09:24:39 +0100
commit897ac6674c64ca94df5b70ea5c6815a296e1d32a (patch)
tree37892782c76bc796df4187061e4396fc3ff362cd /drivers/gpio/gpio-stmpe.c
parentc16bee7897bffc3814390c9279bf01137a6bd595 (diff)
downloadlwn-897ac6674c64ca94df5b70ea5c6815a296e1d32a.tar.gz
lwn-897ac6674c64ca94df5b70ea5c6815a296e1d32a.zip
mfd: stmpe: Rework registers access
this update allows to use registers map as following : regs[reg_index + offset] instead of regs[reg_index] + offset This makes code clearer and will facilitate the addition of STMPE1600 on which LSB and MSB registers are respectively located at addr and addr + 1. Despite for all others STMPE variant, LSB and MSB registers are respectively located in reverse order at addr + 1 and addr. For variant which have 3 registers's bank, we use LSB,CSB and MSB indexes which contains respectively LSB (or LOW), CSB (or MID) and MSB (or HIGH) register addresses (STMPE1801/STMPE24xx). For variant which have 2 registers's bank, we use LSB and CSB indexes only. In this case the CSB index contains the MSB regs address (STMPE 1601). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'drivers/gpio/gpio-stmpe.c')
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