diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2013-01-06 21:52:03 +0530 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@intel.com> | 2013-01-08 02:53:29 -0800 |
| commit | 5ea7caf30debefc1c4319f77146288fd5e92a803 (patch) | |
| tree | 0ce202f3d64bd81ed975231f8f56fcd8d9416427 /drivers/dma/tegra20-apb-dma.c | |
| parent | 1b140908c4cda43c653bb080c244d112e619008f (diff) | |
| download | lwn-5ea7caf30debefc1c4319f77146288fd5e92a803.tar.gz lwn-5ea7caf30debefc1c4319f77146288fd5e92a803.zip | |
dma: tegra: add support for Tegra114 SoC
NVIDIA's Tegra114 has APB DMA controller which has 32 dma channels
and support support channel wise pause control.
Add support for Tegra114 which uses the channel wise pause control
hardware feature.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/tegra20-apb-dma.c')
| -rw-r--r-- | drivers/dma/tegra20-apb-dma.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c index 2c46ac46e7ad..6c144814a896 100644 --- a/drivers/dma/tegra20-apb-dma.c +++ b/drivers/dma/tegra20-apb-dma.c @@ -1217,8 +1217,19 @@ static const struct tegra_dma_chip_data tegra30_dma_chip_data = { .support_channel_pause = false, }; -static const struct of_device_id tegra_dma_of_match[] __devinitconst = { +/* Tegra114 specific DMA controller information */ +static const struct tegra_dma_chip_data tegra114_dma_chip_data = { + .nr_channels = 32, + .max_dma_count = 1024UL * 64, + .support_channel_pause = true, +}; + + +static const struct of_device_id tegra_dma_of_match[] = { { + .compatible = "nvidia,tegra114-apbdma", + .data = &tegra114_dma_chip_data, + }, { .compatible = "nvidia,tegra30-apbdma", .data = &tegra30_dma_chip_data, }, { |