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| author | Thomas Breitung <thomas.breitung@izt-labs.de> | 2017-06-19 16:40:04 +0200 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@intel.com> | 2017-06-22 18:31:35 +0530 |
| commit | ccc077292733f3143b444255fa5ec49a8ff2763b (patch) | |
| tree | f867c7838c806b891adcb7e3c955d5e8bbe74817 /drivers/dma/fsldma.h | |
| parent | 036e9ef8becde736e693be4f4bef56d5b56fc298 (diff) | |
| download | lwn-ccc077292733f3143b444255fa5ec49a8ff2763b.tar.gz lwn-ccc077292733f3143b444255fa5ec49a8ff2763b.zip | |
dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly
The bits of BWC, DAHTS and SAHTS in the DMA mode register must be cleared
before a new value can be or-ed in.
Signed-off-by: Thomas Breitung <thomas.breitung@izt-labs.de>
Signed-off-by: Wolfgang Ocker <weo@reccoware.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/fsldma.h')
| -rw-r--r-- | drivers/dma/fsldma.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h index 31bffccdcc75..4787d485dd76 100644 --- a/drivers/dma/fsldma.h +++ b/drivers/dma/fsldma.h @@ -36,6 +36,10 @@ #define FSL_DMA_MR_DAHE 0x00002000 #define FSL_DMA_MR_SAHE 0x00001000 +#define FSL_DMA_MR_SAHTS_MASK 0x0000C000 +#define FSL_DMA_MR_DAHTS_MASK 0x00030000 +#define FSL_DMA_MR_BWC_MASK 0x0f000000 + /* * Bandwidth/pause control determines how many bytes a given * channel is allowed to transfer before the DMA engine pauses |