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author | Brian Norris <briannorris@chromium.org> | 2022-04-05 18:48:42 -0700 |
---|---|---|
committer | Chanwoo Choi <cw00.choi@samsung.com> | 2022-05-09 03:38:07 +0900 |
commit | 2e691421a2c9e0462175fe98171afa632861b199 (patch) | |
tree | b3a244ec01e25c91a720d4a33a70476fdac2ef8b /drivers/devfreq | |
parent | defec178df76e0caadd4e8ef68f3d655a2088198 (diff) | |
download | lwn-2e691421a2c9e0462175fe98171afa632861b199.tar.gz lwn-2e691421a2c9e0462175fe98171afa632861b199.zip |
PM / devfreq: rk3399_dmc: Block PMU during transitions
See the previous patch ("soc: rockchip: power-domain: Manage resource
conflicts with firmware") for a thorough explanation of the conflicts.
While ARM Trusted Firmware may be modifying memory controller and
power-domain states, we need to block the kernel's power-domain driver.
If the power-domain driver is disabled, there is no resource conflict
and this becomes a no-op.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Diffstat (limited to 'drivers/devfreq')
-rw-r--r-- | drivers/devfreq/rk3399_dmc.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index e494d1497d60..daff40702615 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -21,6 +21,7 @@ #include <linux/rwsem.h> #include <linux/suspend.h> +#include <soc/rockchip/pm_domains.h> #include <soc/rockchip/rk3399_grf.h> #include <soc/rockchip/rockchip_sip.h> @@ -94,6 +95,16 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, mutex_lock(&dmcfreq->lock); /* + * Ensure power-domain transitions don't interfere with ARM Trusted + * Firmware power-domain idling. + */ + err = rockchip_pmu_block(); + if (err) { + dev_err(dev, "Failed to block PMU: %d\n", err); + goto out_unlock; + } + + /* * Some idle parameters may be based on the DDR controller clock, which * is half of the DDR frequency. * pd_idle and standby_idle are based on the controller clock cycle. @@ -198,6 +209,8 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, dmcfreq->volt = target_volt; out: + rockchip_pmu_unblock(); +out_unlock: mutex_unlock(&dmcfreq->lock); return err; } |