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authorSamuel Holland <samuel@sholland.org>2021-11-17 21:18:41 -0600
committerChanwoo Choi <cw00.choi@samsung.com>2021-12-10 15:56:07 +0900
commit8bfd4858b4bba8fec14e4296cbac71aa55260d60 (patch)
tree1d3c0176ccd7fccf07bc5bfb24dffa43af7fc6c7 /drivers/devfreq/Makefile
parent0fcfb00b28c0b7884635dacf38e46d60bf3d4eb1 (diff)
downloadlwn-8bfd4858b4bba8fec14e4296cbac71aa55260d60.tar.gz
lwn-8bfd4858b4bba8fec14e4296cbac71aa55260d60.zip
PM / devfreq: Add a driver for the sun8i/sun50i MBUS
This driver works by adjusting the divider on the DRAM controller's module clock. Thus there is no fixed set of OPPs, only "full speed" down to "quarter speed" (or whatever the maximum divider is on that variant). It makes use of the MDFS hardware in the MBUS, in "DFS" mode, which takes care of updating registers during the critical section while DRAM is inaccessible. This driver should support several sunxi SoCs, starting with the A33, which have a DesignWare DDR3 controller with merged PHY register space and the matching MBUS register layout (so not A63 or later). However, the driver has only been tested on the A64/H5, so those are the only compatibles enabled for now. Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Diffstat (limited to 'drivers/devfreq/Makefile')
-rw-r--r--drivers/devfreq/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index a16333ea7034..0b6be92a25d9 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
+obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
# DEVFREQ Event Drivers