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authorJim Harris <jim.harris@samsung.com>2023-11-03 20:18:34 +0000
committerDan Williams <dan.j.williams@intel.com>2024-01-03 17:55:20 -0800
commitc7ad3dc3649730af483ee1e78be5d0362da25bfe (patch)
treea126e48768c3c60cbfa3e96bbf3fea56f9489f73 /drivers/cxl
parent861deac3b092f37b2c5e6871732f3e11486f7082 (diff)
downloadlwn-c7ad3dc3649730af483ee1e78be5d0362da25bfe.tar.gz
lwn-c7ad3dc3649730af483ee1e78be5d0362da25bfe.zip
cxl/region: fix x9 interleave typo
CXL supports x3, x6 and x12 - not x9. Fixes: 80d10a6cee050 ("cxl/region: Add interleave geometry attributes") Signed-off-by: Jim Harris <jim.harris@samsung.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Link: https://lore.kernel.org/r/169904271254.204936.8580772404462743630.stgit@ubuntu Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl')
-rw-r--r--drivers/cxl/core/region.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index 3e817a6f94c6..76fec47a13a4 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -397,7 +397,7 @@ static ssize_t interleave_ways_store(struct device *dev,
return rc;
/*
- * Even for x3, x9, and x12 interleaves the region interleave must be a
+ * Even for x3, x6, and x12 interleaves the region interleave must be a
* power of 2 multiple of the host bridge interleave.
*/
if (!is_power_of_2(val / cxld->interleave_ways) ||