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| author | Yang Shen <shenyang39@huawei.com> | 2020-11-13 17:32:35 +0800 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2020-11-20 14:45:33 +1100 |
| commit | 1dc440355e472a60a98cb4ec9aa5ec56267a96fc (patch) | |
| tree | 44080516be7b353d6ebe0a1777f73330cb581a15 /drivers/crypto/omap-aes.c | |
| parent | 1201581c57925b8bc2cba8628b61add3d16d4615 (diff) | |
| download | lwn-1dc440355e472a60a98cb4ec9aa5ec56267a96fc.tar.gz lwn-1dc440355e472a60a98cb4ec9aa5ec56267a96fc.zip | |
crypto: hisilicon/zip - add a work_queue for zip irq
The patch 'irqchip/gic-v3-its: Balance initial LPI affinity across CPUs'
set the IRQ to an uncentain CPU. If an IRQ is bound to the CPU used by the
thread which is sending request, the throughput will be just half.
So allocate a 'work_queue' and set as 'WQ_UNBOUND' to do the back half work
on some different CPUS.
Signed-off-by: Yang Shen <shenyang39@huawei.com>
Reviewed-by: Zaibo Xu <xuzaibo@huawei.com>
Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/omap-aes.c')
0 files changed, 0 insertions, 0 deletions