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| author | Horia Geantă <horia.geanta@nxp.com> | 2017-07-18 18:30:47 +0300 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2017-08-03 13:47:13 +0800 |
| commit | 297b9cebd2fc020f0bd3e0aac68b0758ab84e8d8 (patch) | |
| tree | 96d62c45c0716972260998f58d8ecc837be94ed4 /drivers/crypto/caam/regs.h | |
| parent | e28c190db66830c04b403b7eba7f8a5b53c22ffc (diff) | |
| download | lwn-297b9cebd2fc020f0bd3e0aac68b0758ab84e8d8.tar.gz lwn-297b9cebd2fc020f0bd3e0aac68b0758ab84e8d8.zip | |
crypto: caam/jr - add support for DPAA2 parts
Add support for using the caam/jr backend on DPAA2-based SoCs.
These have some particularities we have to account for:
-HW S/G format is different
-Management Complex (MC) firmware initializes / manages (partially)
the CAAM block: MCFGR, QI enablement in QICTL, RNG
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/caam/regs.h')
| -rw-r--r-- | drivers/crypto/caam/regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h index 84d2f838a063..2b5efff9ec3c 100644 --- a/drivers/crypto/caam/regs.h +++ b/drivers/crypto/caam/regs.h @@ -293,6 +293,7 @@ struct caam_perfmon { u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/ #define CTPR_MS_QI_SHIFT 25 #define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT) +#define CTPR_MS_DPAA2 BIT(13) #define CTPR_MS_VIRT_EN_INCL 0x00000001 #define CTPR_MS_VIRT_EN_POR 0x00000002 #define CTPR_MS_PG_SZ_MASK 0x10 |