diff options
| author | Stephen Boyd <sboyd@kernel.org> | 2023-06-26 14:56:06 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-06-26 14:56:06 -0700 |
| commit | 7ed1cefbf169367bae5b356ecd15928b040aeafc (patch) | |
| tree | 4c311306ee73624e8d240822d9e037315a110150 /drivers/clk | |
| parent | ac9a78681b921877518763ba0e89202254349d1b (diff) | |
| parent | e5d10d1d1aa4c7274bf7ff54660832004800655a (diff) | |
| download | lwn-7ed1cefbf169367bae5b356ecd15928b040aeafc.tar.gz lwn-7ed1cefbf169367bae5b356ecd15928b040aeafc.zip | |
Merge tag 'qcom-clk-for-6.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson:
This introduces Global Clock Controller for SDX75, LPASS clock
controllers for SC8280XP, video clock controller for SM8350, SM8450 and
SM8550, GPU clock controller for SM8450 and SM8550, RPMH clock support
for SDX75 and IPQ9574 support in APSS IPQ PLL driver.
Support for branch2 clocks with inverted off-bit is introduced and a
couple of fixes to Alpha PLLs handling of TEST_CTL updates.
The handling of active-only clocks in SMD RPM is improved, to ensure
votes are appropriately placed.
SC7180 camera GDSCs are made children of the titan_top GDSC.
A couple of fixes to the display clocks on QCM2290 and shared RCGs in
GCC are marked as such.
SDCC clocks for IPQ6018 and IPQ5332 are corrected to use floor ops, and
network-related resets on IPQ6018 are updated to cover all bits of each
reset.
Crypto clocks are added to IPQ9574 global clock controller, together
with a few cleanups.
Runtime PM is enabeld for SC8280XP GCC and GPUCC, and SM6375 GPUCC.
A few fixes for MSM8974 multi-media clock controller.
Support for some RCG clocks to be automatically controlled by downstream
branches, and added to SM8450 GCC clocks.
Further Kconfig depdenencies are introduce to avoid building Qualcomm
clock drivers on unrelated architectures.
Lastly, related DeviceTree binding updates are made.
The tail of this is not bisectable, due to the missing DeviceTree
binding include files. Rebase at this point in time is not desirable.
* tag 'qcom-clk-for-6.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (63 commits)
clk: qcom: gcc-sc8280xp: Add runtime PM
clk: qcom: gpucc-sc8280xp: Add runtime PM
clk: qcom: mmcc-msm8974: fix MDSS_GDSC power flags
clk: qcom: gpucc-sm6375: Enable runtime pm
dt-bindings: clock: sm6375-gpucc: Add VDD_GX
clk: qcom: gcc-sm6115: Add missing PLL config properties
clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)
clk: qcom: gcc-ipq6018: remove duplicate initializers
clk: qcom: gcc-ipq9574: Enable crypto clocks
dt-bindings: clock: Add crypto clock and reset definitions
clk: qcom: Add lpass audio clock controller driver for SC8280XP
clk: qcom: Add lpass clock controller driver for SC8280XP
dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP
dt-bindings: clock: Add LPASSCC and reset controller for SC8280XP
dt-bindings: clock: qcom,mmcc: define clocks/clock-names for MSM8226
clk: qcom: gpucc-sm8550: Add support for graphics clock controller
clk: qcom: Add support for SM8450 GPUCC
clk: qcom: gcc-sm8450: Enable hw_clk_ctrl
clk: qcom: rcg2: Make hw_clk_ctrl toggleable
dt-bindings: clock: qcom: Add SM8550 graphics clock controller
...
Diffstat (limited to 'drivers/clk')
30 files changed, 6621 insertions, 345 deletions
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 12be3e2371b3..579749068338 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -57,6 +57,7 @@ config QCOM_CLK_APCC_MSM8996 config QCOM_CLK_APCS_SDX55 tristate "SDX55 and SDX65 APCS Clock Controller" depends on QCOM_APCS_IPC || COMPILE_TEST + depends on ARM || COMPILE_TEST help Support for the APCS Clock Controller on SDX55, SDX65 platforms. The APCS is managing the mux and divider which feeds the CPUs. @@ -100,6 +101,7 @@ config QCOM_CLK_RPMH config APQ_GCC_8084 tristate "APQ8084 Global Clock Controller" + depends on ARM || COMPILE_TEST select QCOM_GDSC help Support for the global clock controller on apq8084 devices. @@ -108,6 +110,7 @@ config APQ_GCC_8084 config APQ_MMCC_8084 tristate "APQ8084 Multimedia Clock Controller" + depends on ARM || COMPILE_TEST select APQ_GCC_8084 select QCOM_GDSC help @@ -159,6 +162,7 @@ config IPQ_GCC_6018 config IPQ_GCC_806X tristate "IPQ806x Global Clock Controller" + depends on ARM || COMPILE_TEST help Support for the global clock controller on ipq806x devices. Say Y if you want to use peripheral devices such as UART, SPI, @@ -166,6 +170,7 @@ config IPQ_GCC_806X config IPQ_LCC_806X tristate "IPQ806x LPASS Clock Controller" + depends on ARM || COMPILE_TEST select IPQ_GCC_806X help Support for the LPASS clock controller on ipq806x devices. @@ -191,6 +196,7 @@ config IPQ_GCC_9574 config MSM_GCC_8660 tristate "MSM8660 Global Clock Controller" + depends on ARM || COMPILE_TEST help Support for the global clock controller on msm8660 devices. Say Y if you want to use peripheral devices such as UART, SPI, @@ -198,6 +204,7 @@ config MSM_GCC_8660 config MSM_GCC_8909 tristate "MSM8909 Global Clock Controller" + depends on ARM || COMPILE_TEST select QCOM_GDSC help Support for the global clock controller on msm8909 devices. @@ -232,6 +239,7 @@ config MSM_GCC_8939 config MSM_GCC_8960 tristate "APQ8064/MSM8960 Global Clock Controller" + depends on ARM || COMPILE_TEST help Support for the global clock controller on apq8064/msm8960 devices. Say Y if you want to use peripheral devices such as UART, SPI, @@ -239,6 +247,7 @@ config MSM_GCC_8960 config MSM_LCC_8960 tristate "APQ8064/MSM8960 LPASS Clock Controller" + depends on ARM || COMPILE_TEST select MSM_GCC_8960 help Support for the LPASS clock controller on apq8064/msm8960 devices. @@ -247,6 +256,7 @@ config MSM_LCC_8960 config MDM_GCC_9607 tristate "MDM9607 Global Clock Controller" + depends on ARM || COMPILE_TEST help Support for the global clock controller on mdm9607 devices. Say Y if you want to use peripheral devices such as UART, SPI, @@ -254,6 +264,7 @@ config MDM_GCC_9607 config MDM_GCC_9615 tristate "MDM9615 Global Clock Controller" + depends on ARM || COMPILE_TEST help Support for the global clock controller on mdm9615 devices. Say Y if you want to use peripheral devices such as UART, SPI, @@ -261,6 +272,7 @@ config MDM_GCC_9615 config MDM_LCC_9615 tristate "MDM9615 LPASS Clock Controller" + depends on ARM || COMPILE_TEST select MDM_GCC_9615 help Support for the LPASS clock controller on mdm9615 devices. @@ -269,6 +281,7 @@ config MDM_LCC_9615 config MSM_MMCC_8960 tristate "MSM8960 Multimedia Clock Controller" + depends on ARM || COMPILE_TEST select MSM_GCC_8960 help Support for the multimedia clock controller on msm8960 devices. @@ -285,6 +298,7 @@ config MSM_GCC_8953 config MSM_GCC_8974 tristate "MSM8974 Global Clock Controller" + depends on ARM || COMPILE_TEST select QCOM_GDSC help Support for the global clock controller on msm8974 devices. @@ -293,6 +307,7 @@ config MSM_GCC_8974 config MSM_MMCC_8974 tristate "MSM8974 Multimedia Clock Controller" + depends on ARM || COMPILE_TEST select MSM_GCC_8974 select QCOM_GDSC help @@ -393,6 +408,7 @@ config QCS_GCC_404 config SC_CAMCC_7180 tristate "SC7180 Camera Clock Controller" + depends on ARM64 || COMPILE_TEST select SC_GCC_7180 help Support for the camera clock controller on Qualcomm Technologies, Inc @@ -402,6 +418,7 @@ config SC_CAMCC_7180 config SC_CAMCC_7280 tristate "SC7280 Camera Clock Controller" + depends on ARM64 || COMPILE_TEST select SC_GCC_7280 help Support for the camera clock controller on Qualcomm Technologies, Inc @@ -411,6 +428,7 @@ config SC_CAMCC_7280 config SC_DISPCC_7180 tristate "SC7180 Display Clock Controller" + depends on ARM64 || COMPILE_TEST select SC_GCC_7180 help Support for the display clock controller on Qualcomm Technologies, Inc @@ -420,6 +438,7 @@ config SC_DISPCC_7180 config SC_DISPCC_7280 tristate "SC7280 Display Clock Controller" + depends on ARM64 || COMPILE_TEST select SC_GCC_7280 help Support for the display clock controller on Qualcomm Technologies, Inc. @@ -429,6 +448,7 @@ config SC_DISPCC_7280 config SC_DISPCC_8280XP tristate "SC8280XP Display Clock Controller" + depends on ARM64 || COMPILE_TEST select SC_GCC_8280XP help Support for the two display clock controllers on Qualcomm @@ -458,6 +478,7 @@ config SC_GCC_7180 tristate "SC7180 Global Clock Controller" select QCOM_GDSC depends on COMMON_CLK_QCOM + depends on ARM64 || COMPILE_TEST help Support for the global clock controller on SC7180 devices. Say Y if you want to use peripheral devices such as UART, SPI, @@ -467,6 +488,7 @@ config SC_GCC_7280 tristate "SC7280 Global Clock Controller" select QCOM_GDSC depends on COMMON_CLK_QCOM + depends on ARM64 || COMPILE_TEST help Support for the global clock controller on SC7280 devices. Say Y if you want to use peripheral devices such as UART, SPI, @@ -476,6 +498,7 @@ config SC_GCC_8180X tristate "SC8180X Global Clock Controller" select QCOM_GDSC depends on COMMON_CLK_QCOM + depends on ARM64 || COMPILE_TEST help Support for the global clock controller on SC8180X devices. Say Y if you want to use peripheral devices such as UART, SPI, @@ -485,6 +508,7 @@ config SC_GCC_8280XP tristate "SC8280XP Global Clock Controller" select QCOM_GDSC depends on COMMON_CLK_QCOM + depends on ARM64 || COMPILE_TEST help Support for the global clock controller on SC8280XP devices. Say Y if you want to use peripheral devices such as UART, SPI, @@ -492,6 +516,7 @@ config SC_GCC_8280XP config SC_GPUCC_7180 tristate "SC7180 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST select SC_GCC_7180 help Support for the graphics clock controller on SC7180 devices. @@ -500,6 +525,7 @@ config SC_GPUCC_7180 config SC_GPUCC_7280 tristate "SC7280 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST select SC_GCC_7280 help Support for the graphics clock controller on SC7280 devices. @@ -508,6 +534,7 @@ config SC_GPUCC_7280 config SC_GPUCC_8280XP tristate "SC8280XP Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST select SC_GCC_8280XP help Support for the graphics clock controller on SC8280XP devices. @@ -516,14 +543,25 @@ config SC_GPUCC_8280XP config SC_LPASSCC_7280 tristate "SC7280 Low Power Audio Subsystem (LPASS) Clock Controller" + depends on ARM64 || COMPILE_TEST select SC_GCC_7280 help Support for the LPASS clock controller on SC7280 devices. Say Y if you want to use the LPASS branch clocks of the LPASS clock controller to reset the LPASS subsystem. +config SC_LPASSCC_8280XP + tristate "SC8280 Low Power Audio Subsystem (LPASS) Clock Controller" + depends on ARM64 || COMPILE_TEST + select SC_GCC_8280XP + help + Support for the LPASS clock controller on SC8280XP devices. + Say Y if you want to use the LPASS branch clocks of the LPASS clock + controller to reset the LPASS subsystem. + config SC_LPASS_CORECC_7180 tristate "SC7180 LPASS Core Clock Controller" + depends on ARM64 || COMPILE_TEST select SC_GCC_7180 help Support for the LPASS(Low Power Audio Subsystem) core clock controller @@ -533,6 +571,7 @@ config SC_LPASS_CORECC_7180 config SC_LPASS_CORECC_7280 tristate "SC7280 LPASS Core & Audio Clock Controller" + depends on ARM64 || COMPILE_TEST select SC_GCC_7280 select QCOM_GDSC help @@ -543,6 +582,7 @@ config SC_LPASS_CORECC_7280 config SC_MSS_7180 tristate "SC7180 Modem Clock Controller" + depends on ARM64 || COMPILE_TEST select SC_GCC_7180 help Support for the Modem Subsystem clock controller on Qualcomm @@ -552,6 +592,7 @@ config SC_MSS_7180 config SC_VIDEOCC_7180 tristate "SC7180 Video Clock Controller" + depends on ARM64 || COMPILE_TEST select SC_GCC_7180 help Support for the video clock controller on SC7180 devices. @@ -560,6 +601,7 @@ config SC_VIDEOCC_7180 config SC_VIDEOCC_7280 tristate "SC7280 Video Clock Controller" + depends on ARM64 || COMPILE_TEST select SC_GCC_7280 help Support for the video clock controller on SC7280 devices. @@ -568,6 +610,7 @@ config SC_VIDEOCC_7280 config SDM_CAMCC_845 tristate "SDM845 Camera Clock Controller" + depends on ARM64 || COMPILE_TEST select SDM_GCC_845 help Support for the camera clock controller on SDM845 devices. @@ -575,6 +618,7 @@ config SDM_CAMCC_845 config SDM_GCC_660 tristate "SDM660 Global Clock Controller" + depends on ARM64 || COMPILE_TEST select QCOM_GDSC help Support for the global clock controller on SDM660 devices. @@ -583,6 +627,7 @@ config SDM_GCC_660 config SDM_MMCC_660 tristate "SDM660 Multimedia Clock Controller" + depends on ARM64 || COMPILE_TEST select SDM_GCC_660 select QCOM_GDSC help @@ -592,6 +637,7 @@ config SDM_MMCC_660 config SDM_GPUCC_660 tristate "SDM660 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST select SDM_GCC_660 select QCOM_GDSC help @@ -623,6 +669,7 @@ config QDU_GCC_1000 config SDM_GCC_845 tristate "SDM845/SDM670 Global Clock Controller" + depends on ARM64 || COMPILE_TEST select QCOM_GDSC help Support for the global clock controller on SDM845 and SDM670 devices. @@ -631,6 +678,7 @@ config SDM_GCC_845 config SDM_GPUCC_845 tristate "SDM845 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST select SDM_GCC_845 help Support for the graphics clock controller on SDM845 devices. @@ -639,6 +687,7 @@ config SDM_GPUCC_845 config SDM_VIDEOCC_845 tristate "SDM845 Video Clock Controller" + depends on ARM64 || COMPILE_TEST select SDM_GCC_845 select QCOM_GDSC help @@ -648,6 +697,7 @@ config SDM_VIDEOCC_845 config SDM_DISPCC_845 tristate "SDM845 Display Clock Controller" + depends on ARM64 || COMPILE_TEST select SDM_GCC_845 help Support for the display clock controller on Qualcomm Technologies, Inc @@ -657,6 +707,7 @@ config SDM_DISPCC_845 config SDM_LPASSCC_845 tristate "SDM845 Low Power Audio Subsystem (LPAAS) Clock Controller" + depends on ARM64 || COMPILE_TEST select SDM_GCC_845 help Support for the LPASS clock controller on SDM845 devices. @@ -665,6 +716,7 @@ config SDM_LPASSCC_845 config SDX_GCC_55 tristate "SDX55 Global Clock Controller" + depends on ARM || COMPILE_TEST select QCOM_GDSC help Support for the global clock controller on SDX55 devices. @@ -673,14 +725,24 @@ config SDX_GCC_55 config SDX_GCC_65 tristate "SDX65 Global Clock Controller" + depends on ARM || COMPILE_TEST select QCOM_GDSC help Support for the global clock controller on SDX65 devices. Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. +config SDX_GCC_75 + tristate "SDX75 Global Clock Controller" + select QCOM_GDSC + help + Support for the global clock controller on SDX75 devices. + Say Y if you want to use peripheral devices such as UART, + SPI, I2C, USB, SD/eMMC, PCIe etc. + config SM_CAMCC_6350 tristate "SM6350 Camera Clock Controller" + depends on ARM64 || COMPILE_TEST select SM_GCC_6350 help Support for the camera clock controller on SM6350 devices. @@ -688,6 +750,7 @@ config SM_CAMCC_6350 config SM_CAMCC_8250 tristate "SM8250 Camera Clock Controller" + depends on ARM64 || COMPILE_TEST select SM_GCC_8250 help Support for the camera clock controller on SM8250 devices. @@ -695,6 +758,7 @@ config SM_CAMCC_8250 config SM_CAMCC_8450 tristate "SM8450 Camera Clock Controller" + depends on ARM64 || COMPILE_TEST select SM_GCC_8450 help Support for the camera clock controller on SM8450 devices. @@ -702,6 +766,7 @@ config SM_CAMCC_8450 config SM_DISPCC_6115 tristate "SM6115 Display Clock Controller" + depends on ARM64 || COMPILE_TEST depends on SM_GCC_6115 help Support for the display clock controller on Qualcomm Technologies, Inc @@ -711,6 +776,7 @@ config SM_DISPCC_6115 config SM_DISPCC_6125 tristate "SM6125 Display Clock Controller" + depends on ARM64 || COMPILE_TEST depends on SM_GCC_6125 help Support for the display clock controller on Qualcomm Technologies, Inc @@ -720,6 +786,7 @@ config SM_DISPCC_6125 config SM_DISPCC_8250 tristate "SM8150/SM8250/SM8350 Display Clock Controller" + depends on ARM64 || COMPILE_TEST depends on SM_GCC_8150 || SM_GCC_8250 || SM_GCC_8350 help Support for the display clock controller on Qualcomm Technologies, Inc @@ -729,6 +796,7 @@ config SM_DISPCC_8250 config SM_DISPCC_6350 tristate "SM6350 Display Clock Controller" + depends on ARM64 || COMPILE_TEST depends on SM_GCC_6350 help Support for the display clock controller on Qualcomm Technologies, Inc @@ -738,6 +806,7 @@ config SM_DISPCC_6350 config SM_DISPCC_6375 tristate "SM6375 Display Clock Controller" + depends on ARM64 || COMPILE_TEST depends on SM_GCC_6375 help Support for the display clock controller on Qualcomm Technologies, Inc @@ -747,6 +816,7 @@ config SM_DISPCC_6375 config SM_DISPCC_8450 tristate "SM8450 Display Clock Controller" + depends on ARM64 || COMPILE_TEST depends on SM_GCC_8450 help Support for the display clock controller on Qualcomm Technologies, Inc @@ -756,6 +826,7 @@ config SM_DISPCC_8450 config SM_DISPCC_8550 tristate "SM8550 Display Clock Controller" + depends on ARM64 || COMPILE_TEST depends on SM_GCC_8550 help Support for the display clock controller on Qualcomm Technologies, Inc @@ -765,6 +836,7 @@ config SM_DISPCC_8550 config SM_GCC_6115 tristate "SM6115 and SM4250 Global Clock Controller" + depends on ARM64 || COMPILE_TEST select QCOM_GDSC help Support for the global clock controller on SM6115 and SM4250 devices. @@ -773,6 +845,7 @@ config SM_GCC_6115 config SM_GCC_6125 tristate "SM6125 Global Clock Controller" + depends on ARM64 || COMPILE_TEST help Support for the global clock controller on SM6125 devices. Say Y if you want to use peripheral devices such as UART, @@ -780,6 +853,7 @@ config SM_GCC_6125 config SM_GCC_6350 tristate "SM6350 Global Clock Controller" + depends on ARM64 || COMPILE_TEST select QCOM_GDSC help Support for the global clock controller on SM6350 devices. @@ -788,6 +862,7 @@ config SM_GCC_6350 config SM_GCC_6375 tristate "SM6375 Global Clock Controller" + depends on ARM64 || COMPILE_TEST select QCOM_GDSC help Support for the global clock controller on SM6375 devices. @@ -804,6 +879,7 @@ config SM_GCC_7150 config SM_GCC_8150 tristate "SM8150 Global Clock Controller" + depends on ARM64 || COMPILE_TEST help Support for the global clock controller on SM8150 devices. Say Y if you want to use peripheral devices such as UART, @@ -811,6 +887,7 @@ config SM_GCC_8150 config SM_GCC_8250 tristate "SM8250 Global Clock Controller" + depends on ARM64 || COMPILE_TEST select QCOM_GDSC help Support for the global clock controller on SM8250 devices. @@ -819,6 +896,7 @@ config SM_GCC_8250 config SM_GCC_8350 tristate "SM8350 Global Clock Controller" + depends on ARM64 || COMPILE_TEST select QCOM_GDSC help Support for the global clock controller on SM8350 devices. @@ -827,6 +905,7 @@ config SM_GCC_8350 config SM_GCC_8450 tristate "SM8450 Global Clock Controller" + depends on ARM64 || COMPILE_TEST select QCOM_GDSC help Support for the global clock controller on SM8450 devices. @@ -835,6 +914,7 @@ config SM_GCC_8450 config SM_GCC_8550 tristate "SM8550 Global Clock Controller" + depends on ARM64 || COMPILE_TEST select QCOM_GDSC help Support for the global clock controller on SM8550 devices. @@ -870,6 +950,7 @@ config SM_GPUCC_6375 config SM_GPUCC_6350 tristate "SM6350 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST select SM_GCC_6350 help Support for the graphics clock controller on SM6350 devices. @@ -878,6 +959,7 @@ config SM_GPUCC_6350 config SM_GPUCC_8150 tristate "SM8150 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST select SM_GCC_8150 help Support for the graphics clock controller on SM8150 devices. @@ -886,6 +968,7 @@ config SM_GPUCC_8150 config SM_GPUCC_8250 tristate "SM8250 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST select SM_GCC_8250 help Support for the graphics clock controller on SM8250 devices. @@ -894,14 +977,32 @@ config SM_GPUCC_8250 config SM_GPUCC_8350 tristate "SM8350 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST select SM_GCC_8350 help Support for the graphics clock controller on SM8350 devices. Say Y if you want to support graphics controller devices and functionality such as 3D graphics. +config SM_GPUCC_8450 + tristate "SM8450 Graphics Clock Controller" + select SM_GCC_8450 + help + Support for the graphics clock controller on SM8450 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + +config SM_GPUCC_8550 + tristate "SM8550 Graphics Clock Controller" + select SM_GCC_8550 + help + Support for the graphics clock controller on SM8550 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_TCSRCC_8550 tristate "SM8550 TCSR Clock Controller" + depends on ARM64 || COMPILE_TEST select QCOM_GDSC help Support for the TCSR clock controller on SM8550 devices. @@ -909,6 +1010,7 @@ config SM_TCSRCC_8550 config SM_VIDEOCC_8150 tristate "SM8150 Video Clock Controller" + depends on ARM64 || COMPILE_TEST select SM_GCC_8150 select QCOM_GDSC help @@ -918,6 +1020,7 @@ config SM_VIDEOCC_8150 config SM_VIDEOCC_8250 tristate "SM8250 Video Clock Controller" + depends on ARM64 || COMPILE_TEST select SM_GCC_8250 select QCOM_GDSC help @@ -925,6 +1028,25 @@ config SM_VIDEOCC_8250 Say Y if you want to support video devices and functionality such as video encode and decode. +config SM_VIDEOCC_8350 + tristate "SM8350 Video Clock Controller" + select SM_GCC_8350 + select QCOM_GDSC + help + Support for the video clock controller on SM8350 devices. + Say Y if you want to support video devices and functionality such as + video encode and decode. + +config SM_VIDEOCC_8550 + tristate "SM8550 Video Clock Controller" + select SM_GCC_8550 + select QCOM_GDSC + help + Support for the video clock controller on Qualcomm Technologies, Inc. + SM8550 devices. + Say Y if you want to support video devices and functionality such as + video encode/decode. + config SPMI_PMIC_CLKDIV tristate "SPMI PMIC clkdiv Support" depends on SPMI || COMPILE_TEST @@ -958,8 +1080,18 @@ config KRAITCC config CLK_GFM_LPASS_SM8250 tristate "SM8250 GFM LPASS Clocks" + depends on ARM64 || COMPILE_TEST help Support for the Glitch Free Mux (GFM) Low power audio subsystem (LPASS) clocks found on SM8250 SoCs. +config SM_VIDEOCC_8450 + tristate "SM8450 Video Clock Controller" + select SM_GCC_8450 + select QCOM_GDSC + help + Support for the video clock controller on Qualcomm Technologies, Inc. + SM8450 devices. + Say Y if you want to support video devices and functionality such as + video encode/decode. endif diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 9ff4c373ad95..e6e294274c35 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -81,6 +81,7 @@ obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o obj-$(CONFIG_SC_GPUCC_8280XP) += gpucc-sc8280xp.o obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o +obj-$(CONFIG_SC_LPASSCC_8280XP) += lpasscc-sc8280xp.o obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o obj-$(CONFIG_SC_LPASS_CORECC_7280) += lpasscorecc-sc7280.o lpassaudiocc-sc7280.o obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o @@ -97,6 +98,7 @@ obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o +obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o @@ -124,9 +126,14 @@ obj-$(CONFIG_SM_GPUCC_6375) += gpucc-sm6375.o obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o +obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o +obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o +obj-$(CONFIG_SM_VIDEOCC_8350) += videocc-sm8350.o +obj-$(CONFIG_SM_VIDEOCC_8450) += videocc-sm8450.o +obj-$(CONFIG_SM_VIDEOCC_8550) += videocc-sm8550.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o obj-$(CONFIG_QCOM_HFPLL) += hfpll.o diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c index cf4f0d340cbf..ce28d882ee78 100644 --- a/drivers/clk/qcom/apss-ipq-pll.c +++ b/drivers/clk/qcom/apss-ipq-pll.c @@ -111,6 +111,18 @@ static const struct alpha_pll_config ipq8074_pll_config = { .test_ctl_hi_val = 0x4000, }; +static const struct alpha_pll_config ipq9574_pll_config = { + .l = 0x3b, + .config_ctl_val = 0x200d4828, + .config_ctl_hi_val = 0x6, + .early_output_mask = BIT(3), + .aux2_output_mask = BIT(2), + .aux_output_mask = BIT(1), + .main_output_mask = BIT(0), + .test_ctl_val = 0x0, + .test_ctl_hi_val = 0x4000, +}; + struct apss_pll_data { int pll_type; struct clk_alpha_pll *pll; @@ -135,6 +147,12 @@ static struct apss_pll_data ipq6018_pll_data = { .pll_config = &ipq6018_pll_config, }; +static struct apss_pll_data ipq9574_pll_data = { + .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, + .pll = &ipq_pll_huayra, + .pll_config = &ipq9574_pll_config, +}; + static const struct regmap_config ipq_pll_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -180,6 +198,7 @@ static const struct of_device_id apss_ipq_pll_match_table[] = { { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data }, { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data }, { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data }, + { .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data }, { } }; MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table); diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c index e2b4804695f3..8a4ba7a19ed1 100644 --- a/drivers/clk/qcom/camcc-sc7180.c +++ b/drivers/clk/qcom/camcc-sc7180.c @@ -1480,12 +1480,21 @@ static struct clk_branch cam_cc_sys_tmr_clk = { }, }; +static struct gdsc titan_top_gdsc = { + .gdscr = 0xb134, + .pd = { + .name = "titan_top_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct gdsc bps_gdsc = { .gdscr = 0x6004, .pd = { .name = "bps_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .parent = &titan_top_gdsc.pd, .flags = HW_CTRL, }; @@ -1495,6 +1504,7 @@ static struct gdsc ife_0_gdsc = { .name = "ife_0_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .parent = &titan_top_gdsc.pd, }; static struct gdsc ife_1_gdsc = { @@ -1503,6 +1513,7 @@ static struct gdsc ife_1_gdsc = { .name = "ife_1_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .parent = &titan_top_gdsc.pd, }; static struct gdsc ipe_0_gdsc = { @@ -1512,15 +1523,9 @@ static struct gdsc ipe_0_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .flags = HW_CTRL, + .parent = &titan_top_gdsc.pd, }; -static struct gdsc titan_top_gdsc = { - .gdscr = 0xb134, - .pd = { - .name = "titan_top_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, -}; static struct clk_hw *cam_cc_sc7180_hws[] = { [CAM_CC_PLL2_OUT_EARLY] = &cam_cc_pll2_out_early.hw, diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index b9f6535a7ba7..e4ef645f65d1 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -55,6 +55,7 @@ #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) +#define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2]) #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) @@ -383,10 +384,21 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); - clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), - config->test_ctl_val); - clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), - config->test_ctl_hi_val); + if (config->test_ctl_mask) + regmap_update_bits(regmap, PLL_TEST_CTL(pll), + config->test_ctl_mask, + config->test_ctl_val); + else + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), + config->test_ctl_val); + + if (config->test_ctl_hi_mask) + regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), + config->test_ctl_hi_mask, + config->test_ctl_hi_val); + else + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), + config->test_ctl_hi_val); if (pll->flags & SUPPORTS_FSM_MODE) qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); @@ -2096,6 +2108,7 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); /* Disable PLL output */ regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index d07b17186b90..e4bd863027ab 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -123,8 +123,11 @@ struct alpha_pll_config { u32 user_ctl_hi_val; u32 user_ctl_hi1_val; u32 test_ctl_val; + u32 test_ctl_mask; u32 test_ctl_hi_val; + u32 test_ctl_hi_mask; u32 test_ctl_hi1_val; + u32 test_ctl_hi2_val; u32 main_output_mask; u32 aux_output_mask; u32 aux2_output_mask; diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index ca896ebf7e1b..fc4735f74f0f 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -43,6 +43,7 @@ static bool clk_branch2_check_halt(const struct clk_branch *br, bool enabling) { u32 val; u32 mask; + bool invert = (br->halt_check == BRANCH_HALT_ENABLE); mask = CBCR_NOC_FSM_STATUS; mask |= CBCR_CLK_OFF; @@ -51,11 +52,10 @@ static bool clk_branch2_check_halt(const struct clk_branch *br, bool enabling) if (enabling) { val &= mask; - return (val & CBCR_CLK_OFF) == 0 || + return (val & CBCR_CLK_OFF) == (invert ? CBCR_CLK_OFF : 0) || FIELD_GET(CBCR_NOC_FSM_STATUS, val) == FSM_STATUS_ON; - } else { - return val & CBCR_CLK_OFF; } + return (val & CBCR_CLK_OFF) == (invert ? 0 : CBCR_CLK_OFF); } static int clk_branch_wait(const struct clk_branch *br, bool enabling, diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 01581f4d2c39..e6d84c8c7989 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -141,6 +141,7 @@ extern const struct clk_ops clk_dyn_rcg_ops; * @clkr: regmap clock handle * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG * @parked_cfg: cached value of the CFG register for parked RCGs + * @hw_clk_ctrl: whether to enable hardware clock control */ struct clk_rcg2 { u32 cmd_rcgr; @@ -152,6 +153,7 @@ struct clk_rcg2 { struct clk_regmap clkr; u8 cfg_off; u32 parked_cfg; + bool hw_clk_ctrl; }; #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 76551534f10d..e22baf3a7112 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -325,6 +325,8 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f, cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; if (rcg->mnd_width && f->n && (f->m != f->n)) cfg |= CFG_MODE_DUAL_EDGE; + if (rcg->hw_clk_ctrl) + cfg |= CFG_HW_CLK_CTRL_MASK; *_cfg &= ~mask; *_cfg |= cfg; diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 45ee370f3307..86572570bc54 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -700,6 +700,24 @@ static const struct clk_rpmh_desc clk_rpmh_qdu1000 = { .num_clks = ARRAY_SIZE(qdu1000_rpmh_clocks), }; +static struct clk_hw *sdx75_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, + [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sdx75 = { + .clks = sdx75_rpmh_clocks, + .num_clks = ARRAY_SIZE(sdx75_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) { @@ -792,6 +810,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,sdm670-rpmh-clk", .data = &clk_rpmh_sdm670}, { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55}, { .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65}, + { .compatible = "qcom,sdx75-rpmh-clk", .data = &clk_rpmh_sdx75}, { .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350}, { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150}, { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 887b945a6fb7..e4de74b68797 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -67,7 +67,7 @@ type, r_id, key) #define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, _name, _active,\ - type, r_id, r, key) \ + type, r_id, r, key, ao_flags) \ static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \ .rpm_res_type = (type), \ @@ -102,12 +102,13 @@ .name = "xo_board", \ }, \ .num_parents = 1, \ + .flags = (ao_flags), \ }, \ } #define __DEFINE_CLK_SMD_RPM_BRANCH(_name, _active, type, r_id, r, key) \ __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(/* empty */, \ - _name, _active, type, r_id, r, key) + _name, _active, type, r_id, r, key, 0) #define DEFINE_CLK_SMD_RPM(_name, type, r_id) \ __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ @@ -126,12 +127,12 @@ #define DEFINE_CLK_SMD_RPM_BRANCH(_name, type, r_id, r) \ __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \ _name##_clk, _name##_a_clk, \ - type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE) + type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE, 0) -#define DEFINE_CLK_SMD_RPM_BRANCH_A(_name, type, r_id, r) \ +#define DEFINE_CLK_SMD_RPM_BRANCH_A(_name, type, r_id, r, ao_flags) \ __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \ _name, _name##_a, type, \ - r_id, r, QCOM_RPM_SMD_KEY_ENABLE) + r_id, r, QCOM_RPM_SMD_KEY_ENABLE, ao_flags) #define DEFINE_CLK_SMD_RPM_QDSS(_name, type, r_id) \ __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ @@ -146,7 +147,7 @@ __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, \ _name, _name##_a, \ QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ - QCOM_RPM_KEY_SOFTWARE_ENABLE) + QCOM_RPM_KEY_SOFTWARE_ENABLE, 0) #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_name, r_id, r) \ DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r); \ @@ -156,6 +157,8 @@ #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw) +static struct qcom_smd_rpm *rpmcc_smd_rpm; + struct clk_smd_rpm { const int rpm_res_type; const int rpm_key; @@ -166,7 +169,6 @@ struct clk_smd_rpm { struct clk_smd_rpm *peer; struct clk_hw hw; unsigned long rate; - struct qcom_smd_rpm *rpm; }; struct clk_smd_rpm_req { @@ -178,6 +180,7 @@ struct clk_smd_rpm_req { struct rpm_smd_clk_desc { struct clk_smd_rpm **clks; size_t num_clks; + bool scaling_before_handover; }; static DEFINE_MUTEX(rpm_smd_clk_lock); @@ -191,12 +194,12 @@ static int clk_smd_rpm_handoff(struct clk_smd_rpm *r) .value = cpu_to_le32(r->branch ? 1 : INT_MAX), }; - ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE, + ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE, r->rpm_res_type, r->rpm_clk_id, &req, sizeof(req)); if (ret) return ret; - ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE, + ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE, r->rpm_res_type, r->rpm_clk_id, &req, sizeof(req)); if (ret) @@ -214,7 +217,7 @@ static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r, .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ }; - return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE, + return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE, r->rpm_res_type, r->rpm_clk_id, &req, sizeof(req)); } @@ -228,7 +231,7 @@ static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r, .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ }; - return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE, + return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE, r->rpm_res_type, r->rpm_clk_id, &req, sizeof(req)); } @@ -395,7 +398,7 @@ static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw, return r->rate; } -static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm) +static int clk_smd_rpm_enable_scaling(void) { int ret; struct clk_smd_rpm_req req = { @@ -404,7 +407,7 @@ static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm) .value = cpu_to_le32(1), }; - ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE, + ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE, QCOM_SMD_RPM_MISC_CLK, QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); if (ret) { @@ -412,7 +415,7 @@ static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm) return ret; } - ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE, + ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE, QCOM_SMD_RPM_MISC_CLK, QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); if (ret) { @@ -438,10 +441,11 @@ static const struct clk_ops clk_smd_rpm_branch_ops = { .recalc_rate = clk_smd_rpm_recalc_rate, }; -DEFINE_CLK_SMD_RPM_BRANCH_A(bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); +/* Disabling BI_TCXO_AO could gate the root clock source of the entire system. */ +DEFINE_CLK_SMD_RPM_BRANCH_A(bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000, CLK_IS_CRITICAL); DEFINE_CLK_SMD_RPM_BRANCH(qdss, QCOM_SMD_RPM_MISC_CLK, 1, 19200000); DEFINE_CLK_SMD_RPM_QDSS(qdss, QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_BRANCH_A(bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1); +DEFINE_CLK_SMD_RPM_BRANCH_A(bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1, 0); DEFINE_CLK_SMD_RPM_BRANCH(mss_cfg_ahb, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); @@ -693,6 +697,7 @@ static struct clk_smd_rpm *msm8974_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { .clks = msm8974_clks, .num_clks = ARRAY_SIZE(msm8974_clks), + .scaling_before_handover = true, }; static struct clk_smd_rpm *msm8976_clks[] = { @@ -1301,12 +1306,11 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) { int ret; size_t num_clks, i; - struct qcom_smd_rpm *rpm; struct clk_smd_rpm **rpm_smd_clks; const struct rpm_smd_clk_desc *desc; - rpm = dev_get_drvdata(pdev->dev.parent); - if (!rpm) { + rpmcc_smd_rpm = dev_get_drvdata(pdev->dev.parent); + if (!rpmcc_smd_rpm) { dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n"); return -ENODEV; } @@ -1318,20 +1322,26 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) rpm_smd_clks = desc->clks; num_clks = desc->num_clks; + if (desc->scaling_before_handover) { + ret = clk_smd_rpm_enable_scaling(); + if (ret) + goto err; + } + for (i = 0; i < num_clks; i++) { if (!rpm_smd_clks[i]) continue; - rpm_smd_clks[i]->rpm = rpm; - ret = clk_smd_rpm_handoff(rpm_smd_clks[i]); if (ret) goto err; } - ret = clk_smd_rpm_enable_scaling(rpm); - if (ret) - goto err; + if (!desc->scaling_before_handover) { + ret = clk_smd_rpm_enable_scaling(); + if (ret) + goto err; + } for (i = 0; i < num_clks; i++) { if (!rpm_smd_clks[i]) diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c index e9cfe41c0442..44dd5cfcc150 100644 --- a/drivers/clk/qcom/dispcc-qcm2290.c +++ b/drivers/clk/qcom/dispcc-qcm2290.c @@ -24,9 +24,11 @@ enum { P_BI_TCXO, + P_BI_TCXO_AO, P_DISP_CC_PLL0_OUT_MAIN, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, + P_GPLL0_OUT_DIV, P_GPLL0_OUT_MAIN, P_SLEEP_CLK, }; @@ -82,8 +84,8 @@ static const struct clk_parent_data disp_cc_parent_data_1[] = { }; static const struct parent_map disp_cc_parent_map_2[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 4 }, + { P_BI_TCXO_AO, 0 }, + { P_GPLL0_OUT_DIV, 4 }, }; static const struct clk_parent_data disp_cc_parent_data_2[] = { @@ -151,9 +153,9 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { }; static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(19200000, P_BI_TCXO_AO, 1, 0, 0), + F(37500000, P_GPLL0_OUT_DIV, 8, 0, 0), + F(75000000, P_GPLL0_OUT_DIV, 4, 0, 0), { } }; diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index bdb4a0a11d07..a75ab88ed14c 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -20,8 +20,8 @@ #include "reset.h" enum { - DT_SLEEP_CLK, DT_XO, + DT_SLEEP_CLK, DT_PCIE_2LANE_PHY_PIPE_CLK, DT_PCIE_2LANE_PHY_PIPE_CLK_X1, DT_USB_PCIE_WRAPPER_PIPE_CLK, @@ -366,7 +366,7 @@ static struct clk_rcg2 gcc_adss_pwm_clk_src = { }; static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] = { - F(480000000, P_GPLL4_OUT_MAIN, 2.5, 0, 0), + F(480000000, P_GPLL4_OUT_AUX, 2.5, 0, 0), F(533333333, P_GPLL0_OUT_MAIN, 1.5, 0, 0), { } }; @@ -963,7 +963,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { .name = "gcc_sdcc1_apps_clk_src", .parent_data = gcc_parent_data_9, .num_parents = ARRAY_SIZE(gcc_parent_data_9), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c index 3f9c2f61a5d9..86b43175b042 100644 --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c @@ -26,8 +26,6 @@ #include "clk-regmap-mux.h" #include "reset.h" -#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } - enum { P_XO, P_BIAS_PLL, @@ -1654,7 +1652,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .name = "sdcc1_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, .num_parents = 4, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; @@ -4151,15 +4149,18 @@ static struct clk_branch gcc_dcc_clk = { static const struct alpha_pll_config ubi32_pll_config = { .l = 0x3e, - .alpha = 0x57, - .config_ctl_val = 0x240d6aa8, - .config_ctl_hi_val = 0x3c2, + .alpha = 0x6667, + .config_ctl_val = 0x240d4828, + .config_ctl_hi_val = 0x6, .main_output_mask = BIT(0), .aux_output_mask = BIT(1), .pre_div_val = 0x0, .pre_div_mask = BIT(12), .post_div_val = 0x0, .post_div_mask = GENMASK(9, 8), + .alpha_en_mask = BIT(24), + .test_ctl_val = 0x1C0000C0, + .test_ctl_hi_val = 0x4000, }; static const struct alpha_pll_config nss_crypto_pll_config = { @@ -4517,24 +4518,24 @@ static const struct qcom_reset_map gcc_ipq6018_resets[] = { [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 }, [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 }, [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 }, - [GCC_PPE_FULL_RESET] = { 0x68014, 0 }, - [GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0 }, + [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 }, + [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 }, [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 }, - [GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0 }, + [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 }, [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 }, - [GCC_EDMA_HW_RESET] = { 0x68014, 0 }, - [GCC_NSSPORT1_RESET] = { 0x68014, 0 }, - [GCC_NSSPORT2_RESET] = { 0x68014, 0 }, - [GCC_NSSPORT3_RESET] = { 0x68014, 0 }, - [GCC_NSSPORT4_RESET] = { 0x68014, 0 }, - [GCC_NSSPORT5_RESET] = { 0x68014, 0 }, - [GCC_UNIPHY0_PORT1_ARES] = { 0x56004, 0 }, - [GCC_UNIPHY0_PORT2_ARES] = { 0x56004, 0 }, - [GCC_UNIPHY0_PORT3_ARES] = { 0x56004, 0 }, - [GCC_UNIPHY0_PORT4_ARES] = { 0x56004, 0 }, - [GCC_UNIPHY0_PORT5_ARES] = { 0x56004, 0 }, - [GCC_UNIPHY0_PORT_4_5_RESET] = { 0x56004, 0 }, - [GCC_UNIPHY0_PORT_4_RESET] = { 0x56004, 0 }, + [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 }, + [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 }, + [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c }, + [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 }, + [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 }, + [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 }, + [GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 }, + [GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 }, + [GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 }, + [GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 }, + [GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 }, + [GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 }, + [GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 }, [GCC_LPASS_BCR] = {0x1F000, 0}, [GCC_UBI32_TBU_BCR] = {0x65000, 0}, [GCC_LPASS_TBU_BCR] = {0x6C000, 0}, diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index b2a2d618a5ec..6914f962c893 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -3,24 +3,24 @@ * Copyright (c) 2023 The Linux Foundation. All rights reserved. */ +#include <linux/clk-provider.h> #include <linux/kernel.h> -#include <linux/err.h> -#include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/regmap.h> -#include <linux/reset-controller.h> #include <dt-bindings/clock/qcom,ipq9574-gcc.h> #include <dt-bindings/reset/qcom,ipq9574-gcc.h> -#include "clk-rcg.h" -#include "clk-branch.h" #include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" #include "clk-regmap-phy-mux.h" +#include "common.h" #include "reset.h" /* Need to match the order of clocks in DT binding */ @@ -69,7 +69,7 @@ static struct clk_alpha_pll gpll0_main = { .clkr = { .enable_reg = 0x0b000, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gpll0_main", .parent_data = gcc_xo_data, .num_parents = ARRAY_SIZE(gcc_xo_data), @@ -81,7 +81,7 @@ static struct clk_alpha_pll gpll0_main = { static struct clk_fixed_factor gpll0_out_main_div2 = { .mult = 1, .div = 2, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gpll0_out_main_div2", .parent_hws = (const struct clk_hw *[]) { &gpll0_main.clkr.hw @@ -96,7 +96,7 @@ static struct clk_alpha_pll_postdiv gpll0 = { .offset = 0x20000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 4, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "gpll0", .parent_hws = (const struct clk_hw *[]) { &gpll0_main.clkr.hw @@ -113,7 +113,7 @@ static struct clk_alpha_pll gpll4_main = { .clkr = { .enable_reg = 0x0b000, .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gpll4_main", .parent_data = gcc_xo_data, .num_parents = ARRAY_SIZE(gcc_xo_data), @@ -126,7 +126,7 @@ static struct clk_alpha_pll_postdiv gpll4 = { .offset = 0x22000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 4, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "gpll4", .parent_hws = (const struct clk_hw *[]) { &gpll4_main.clkr.hw @@ -143,7 +143,7 @@ static struct clk_alpha_pll gpll2_main = { .clkr = { .enable_reg = 0x0b000, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gpll2_main", .parent_data = gcc_xo_data, .num_parents = ARRAY_SIZE(gcc_xo_data), @@ -156,7 +156,7 @@ static struct clk_alpha_pll_postdiv gpll2 = { .offset = 0x21000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 4, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "gpll2", .parent_hws = (const struct clk_hw *[]) { &gpll2_main.clkr.hw @@ -172,7 +172,7 @@ static struct clk_branch gcc_sleep_clk_src = { .clkr = { .enable_reg = 0x3400c, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_sleep_clk_src", .parent_data = gcc_sleep_clk_data, .num_parents = ARRAY_SIZE(gcc_sleep_clk_data), @@ -420,7 +420,7 @@ static struct clk_rcg2 apss_ahb_clk_src = { .freq_tbl = ftbl_apss_ahb_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "apss_ahb_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -438,7 +438,7 @@ static struct clk_rcg2 apss_axi_clk_src = { .freq_tbl = ftbl_apss_axi_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_div2_gpll0_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "apss_axi_clk_src", .parent_data = gcc_xo_gpll0_gpll0_div2_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_div2_gpll0), @@ -458,7 +458,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_qup1_i2c_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -483,7 +483,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_qup1_spi_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -496,7 +496,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_qup2_i2c_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -510,7 +510,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_qup2_spi_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -523,7 +523,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_qup3_i2c_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -537,7 +537,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_qup3_spi_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -550,7 +550,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_qup4_i2c_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -564,7 +564,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_qup4_spi_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -577,7 +577,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_qup5_i2c_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -591,7 +591,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_qup5_spi_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -604,7 +604,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_qup6_i2c_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -618,7 +618,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_qup6_spi_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -650,7 +650,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .mnd_width = 16, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_uart1_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -664,7 +664,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .mnd_width = 16, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_uart2_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -678,7 +678,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .mnd_width = 16, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_uart3_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -692,7 +692,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = { .mnd_width = 16, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_uart4_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -706,7 +706,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = { .mnd_width = 16, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_uart5_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -720,7 +720,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { .mnd_width = 16, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "blsp1_uart6_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -728,13 +728,48 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = { + F(160000000, P_GPLL0, 5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_crypto_clk_src = { + .cmd_rcgr = 0x16004, + .freq_tbl = ftbl_gcc_crypto_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_crypto_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_crypto_clk = { + .halt_reg = 0x1600c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x0b004, + .enable_mask = BIT(14), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_crypto_clk", + .parent_hws = (const struct clk_hw *[]) { + &gcc_crypto_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_apss_ahb_clk = { .halt_reg = 0x24018, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x0b004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_apss_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &apss_ahb_clk_src.clkr.hw @@ -752,7 +787,7 @@ static struct clk_branch gcc_apss_axi_clk = { .clkr = { .enable_reg = 0x0b004, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_apss_axi_clk", .parent_hws = (const struct clk_hw *[]) { &apss_axi_clk_src.clkr.hw @@ -769,7 +804,7 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { .clkr = { .enable_reg = 0x2024, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_qup1_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup1_i2c_apps_clk_src.clkr.hw @@ -786,7 +821,7 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { .clkr = { .enable_reg = 0x02020, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_qup1_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup1_spi_apps_clk_src.clkr.hw @@ -803,7 +838,7 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { .clkr = { .enable_reg = 0x03024, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_qup2_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup2_i2c_apps_clk_src.clkr.hw @@ -820,7 +855,7 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { .clkr = { .enable_reg = 0x03020, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_qup2_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup2_spi_apps_clk_src.clkr.hw @@ -837,7 +872,7 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { .clkr = { .enable_reg = 0x04024, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_qup3_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup3_i2c_apps_clk_src.clkr.hw @@ -854,7 +889,7 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { .clkr = { .enable_reg = 0x04020, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_qup3_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup3_spi_apps_clk_src.clkr.hw @@ -871,7 +906,7 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { .clkr = { .enable_reg = 0x05024, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_qup4_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup4_i2c_apps_clk_src.clkr.hw @@ -888,7 +923,7 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { .clkr = { .enable_reg = 0x05020, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_qup4_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup4_spi_apps_clk_src.clkr.hw @@ -905,7 +940,7 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { .clkr = { .enable_reg = 0x06024, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_qup5_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup5_i2c_apps_clk_src.clkr.hw @@ -922,7 +957,7 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { .clkr = { .enable_reg = 0x06020, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_qup5_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup5_spi_apps_clk_src.clkr.hw @@ -939,7 +974,7 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { .clkr = { .enable_reg = 0x07024, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_qup6_i2c_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup6_i2c_apps_clk_src.clkr.hw @@ -956,7 +991,7 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { .clkr = { .enable_reg = 0x07020, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_qup6_spi_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_qup6_spi_apps_clk_src.clkr.hw @@ -973,7 +1008,7 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = { .clkr = { .enable_reg = 0x02040, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_uart1_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_uart1_apps_clk_src.clkr.hw @@ -990,7 +1025,7 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = { .clkr = { .enable_reg = 0x03040, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_uart2_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_uart2_apps_clk_src.clkr.hw @@ -1007,7 +1042,7 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = { .clkr = { .enable_reg = 0x04054, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_uart3_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_uart3_apps_clk_src.clkr.hw @@ -1024,7 +1059,7 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = { .clkr = { .enable_reg = 0x05040, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_uart4_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_uart4_apps_clk_src.clkr.hw @@ -1041,7 +1076,7 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = { .clkr = { .enable_reg = 0x06040, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_uart5_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_uart5_apps_clk_src.clkr.hw @@ -1058,7 +1093,7 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = { .clkr = { .enable_reg = 0x07040, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_uart6_apps_clk", .parent_hws = (const struct clk_hw *[]) { &blsp1_uart6_apps_clk_src.clkr.hw @@ -1080,7 +1115,7 @@ static struct clk_rcg2 pcie0_axi_m_clk_src = { .freq_tbl = ftbl_pcie0_axi_m_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll4_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "pcie0_axi_m_clk_src", .parent_data = gcc_xo_gpll0_gpll4, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), @@ -1093,7 +1128,7 @@ static struct clk_branch gcc_pcie0_axi_m_clk = { .clkr = { .enable_reg = 0x28038, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie0_axi_m_clk", .parent_hws = (const struct clk_hw *[]) { &pcie0_axi_m_clk_src.clkr.hw @@ -1110,7 +1145,7 @@ static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = { .clkr = { .enable_reg = 0x2e07c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_anoc_pcie0_1lane_m_clk", .parent_hws = (const struct clk_hw *[]) { &pcie0_axi_m_clk_src.clkr.hw @@ -1127,7 +1162,7 @@ static struct clk_rcg2 pcie1_axi_m_clk_src = { .freq_tbl = ftbl_pcie0_axi_m_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll4_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "pcie1_axi_m_clk_src", .parent_data = gcc_xo_gpll0_gpll4, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), @@ -1140,7 +1175,7 @@ static struct clk_branch gcc_pcie1_axi_m_clk = { .clkr = { .enable_reg = 0x29038, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie1_axi_m_clk", .parent_hws = (const struct clk_hw *[]) { &pcie1_axi_m_clk_src.clkr.hw @@ -1157,7 +1192,7 @@ static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = { .clkr = { .enable_reg = 0x2e08c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_anoc_pcie1_1lane_m_clk", .parent_hws = (const struct clk_hw *[]) { &pcie1_axi_m_clk_src.clkr.hw @@ -1179,7 +1214,7 @@ static struct clk_rcg2 pcie2_axi_m_clk_src = { .freq_tbl = ftbl_pcie2_axi_m_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "pcie2_axi_m_clk_src", .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk), @@ -1192,7 +1227,7 @@ static struct clk_branch gcc_pcie2_axi_m_clk = { .clkr = { .enable_reg = 0x2a038, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie2_axi_m_clk", .parent_hws = (const struct clk_hw *[]) { &pcie2_axi_m_clk_src.clkr.hw @@ -1209,7 +1244,7 @@ static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = { .clkr = { .enable_reg = 0x2e080, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_anoc_pcie2_2lane_m_clk", .parent_hws = (const struct clk_hw *[]) { &pcie2_axi_m_clk_src.clkr.hw @@ -1226,7 +1261,7 @@ static struct clk_rcg2 pcie3_axi_m_clk_src = { .freq_tbl = ftbl_pcie2_axi_m_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "pcie3_axi_m_clk_src", .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk), @@ -1239,7 +1274,7 @@ static struct clk_branch gcc_pcie3_axi_m_clk = { .clkr = { .enable_reg = 0x2b038, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie3_axi_m_clk", .parent_hws = (const struct clk_hw *[]) { &pcie3_axi_m_clk_src.clkr.hw @@ -1256,7 +1291,7 @@ static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = { .clkr = { .enable_reg = 0x2e090, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_anoc_pcie3_2lane_m_clk", .parent_hws = (const struct clk_hw *[]) { &pcie3_axi_m_clk_src.clkr.hw @@ -1273,7 +1308,7 @@ static struct clk_rcg2 pcie0_axi_s_clk_src = { .freq_tbl = ftbl_pcie0_axi_m_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll4_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "pcie0_axi_s_clk_src", .parent_data = gcc_xo_gpll0_gpll4, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), @@ -1286,7 +1321,7 @@ static struct clk_branch gcc_pcie0_axi_s_clk = { .clkr = { .enable_reg = 0x2803c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie0_axi_s_clk", .parent_hws = (const struct clk_hw *[]) { &pcie0_axi_s_clk_src.clkr.hw @@ -1303,7 +1338,7 @@ static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { .clkr = { .enable_reg = 0x28040, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie0_axi_s_bridge_clk", .parent_hws = (const struct clk_hw *[]) { &pcie0_axi_s_clk_src.clkr.hw @@ -1320,7 +1355,7 @@ static struct clk_branch gcc_snoc_pcie0_1lane_s_clk = { .clkr = { .enable_reg = 0x2e048, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_snoc_pcie0_1lane_s_clk", .parent_hws = (const struct clk_hw *[]) { &pcie0_axi_s_clk_src.clkr.hw @@ -1337,7 +1372,7 @@ static struct clk_rcg2 pcie1_axi_s_clk_src = { .freq_tbl = ftbl_pcie0_axi_m_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll4_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "pcie1_axi_s_clk_src", .parent_data = gcc_xo_gpll0_gpll4, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), @@ -1350,7 +1385,7 @@ static struct clk_branch gcc_pcie1_axi_s_clk = { .clkr = { .enable_reg = 0x2903c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie1_axi_s_clk", .parent_hws = (const struct clk_hw *[]) { &pcie1_axi_s_clk_src.clkr.hw @@ -1367,7 +1402,7 @@ static struct clk_branch gcc_pcie1_axi_s_bridge_clk = { .clkr = { .enable_reg = 0x29040, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie1_axi_s_bridge_clk", .parent_hws = (const struct clk_hw *[]) { &pcie1_axi_s_clk_src.clkr.hw @@ -1384,7 +1419,7 @@ static struct clk_branch gcc_snoc_pcie1_1lane_s_clk = { .clkr = { .enable_reg = 0x2e04c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_snoc_pcie1_1lane_s_clk", .parent_hws = (const struct clk_hw *[]) { &pcie1_axi_s_clk_src.clkr.hw @@ -1401,7 +1436,7 @@ static struct clk_rcg2 pcie2_axi_s_clk_src = { .freq_tbl = ftbl_pcie0_axi_m_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll4_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "pcie2_axi_s_clk_src", .parent_data = gcc_xo_gpll0_gpll4, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), @@ -1414,7 +1449,7 @@ static struct clk_branch gcc_pcie2_axi_s_clk = { .clkr = { .enable_reg = 0x2a03c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie2_axi_s_clk", .parent_hws = (const struct clk_hw *[]) { &pcie2_axi_s_clk_src.clkr.hw @@ -1431,7 +1466,7 @@ static struct clk_branch gcc_pcie2_axi_s_bridge_clk = { .clkr = { .enable_reg = 0x2a040, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie2_axi_s_bridge_clk", .parent_hws = (const struct clk_hw *[]) { &pcie2_axi_s_clk_src.clkr.hw @@ -1448,7 +1483,7 @@ static struct clk_branch gcc_snoc_pcie2_2lane_s_clk = { .clkr = { .enable_reg = 0x2e050, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_snoc_pcie2_2lane_s_clk", .parent_hws = (const struct clk_hw *[]) { &pcie2_axi_s_clk_src.clkr.hw @@ -1465,7 +1500,7 @@ static struct clk_rcg2 pcie3_axi_s_clk_src = { .freq_tbl = ftbl_pcie0_axi_m_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll4_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "pcie3_axi_s_clk_src", .parent_data = gcc_xo_gpll0_gpll4, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), @@ -1478,7 +1513,7 @@ static struct clk_branch gcc_pcie3_axi_s_clk = { .clkr = { .enable_reg = 0x2b03c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie3_axi_s_clk", .parent_hws = (const struct clk_hw *[]) { &pcie3_axi_s_clk_src.clkr.hw @@ -1495,7 +1530,7 @@ static struct clk_branch gcc_pcie3_axi_s_bridge_clk = { .clkr = { .enable_reg = 0x2b040, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie3_axi_s_bridge_clk", .parent_hws = (const struct clk_hw *[]) { &pcie3_axi_s_clk_src.clkr.hw @@ -1512,7 +1547,7 @@ static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = { .clkr = { .enable_reg = 0x2e054, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_snoc_pcie3_2lane_s_clk", .parent_hws = (const struct clk_hw *[]) { &pcie3_axi_s_clk_src.clkr.hw @@ -1527,7 +1562,7 @@ static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = { static struct clk_regmap_phy_mux pcie0_pipe_clk_src = { .reg = 0x28064, .clkr = { - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "pcie0_pipe_clk_src", .parent_data = &(const struct clk_parent_data) { .index = DT_PCIE30_PHY0_PIPE_CLK, @@ -1541,7 +1576,7 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = { static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { .reg = 0x29064, .clkr = { - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "pcie1_pipe_clk_src", .parent_data = &(const struct clk_parent_data) { .index = DT_PCIE30_PHY1_PIPE_CLK, @@ -1555,7 +1590,7 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { .reg = 0x2a064, .clkr = { - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "pcie2_pipe_clk_src", .parent_data = &(const struct clk_parent_data) { .index = DT_PCIE30_PHY2_PIPE_CLK, @@ -1569,7 +1604,7 @@ static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { .reg = 0x2b064, .clkr = { - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "pcie3_pipe_clk_src", .parent_data = &(const struct clk_parent_data) { .index = DT_PCIE30_PHY3_PIPE_CLK, @@ -1591,7 +1626,7 @@ static struct clk_rcg2 pcie0_rchng_clk_src = { .freq_tbl = ftbl_pcie_rchng_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "pcie0_rchng_clk_src", .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), @@ -1604,7 +1639,7 @@ static struct clk_branch gcc_pcie0_rchng_clk = { .clkr = { .enable_reg = 0x28028, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie0_rchng_clk", .parent_hws = (const struct clk_hw *[]) { &pcie0_rchng_clk_src.clkr.hw @@ -1622,7 +1657,7 @@ static struct clk_rcg2 pcie1_rchng_clk_src = { .freq_tbl = ftbl_pcie_rchng_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "pcie1_rchng_clk_src", .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), @@ -1635,7 +1670,7 @@ static struct clk_branch gcc_pcie1_rchng_clk = { .clkr = { .enable_reg = 0x29028, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie1_rchng_clk", .parent_hws = (const struct clk_hw *[]) { &pcie1_rchng_clk_src.clkr.hw @@ -1652,7 +1687,7 @@ static struct clk_rcg2 pcie2_rchng_clk_src = { .freq_tbl = ftbl_pcie_rchng_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "pcie2_rchng_clk_src", .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), @@ -1665,7 +1700,7 @@ static struct clk_branch gcc_pcie2_rchng_clk = { .clkr = { .enable_reg = 0x2a028, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie2_rchng_clk", .parent_hws = (const struct clk_hw *[]) { &pcie2_rchng_clk_src.clkr.hw @@ -1682,7 +1717,7 @@ static struct clk_rcg2 pcie3_rchng_clk_src = { .freq_tbl = ftbl_pcie_rchng_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "pcie3_rchng_clk_src", .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), @@ -1695,7 +1730,7 @@ static struct clk_branch gcc_pcie3_rchng_clk = { .clkr = { .enable_reg = 0x2b028, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie3_rchng_clk", .parent_hws = (const struct clk_hw *[]) { &pcie3_rchng_clk_src.clkr.hw @@ -1718,7 +1753,7 @@ static struct clk_rcg2 pcie_aux_clk_src = { .mnd_width = 16, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "pcie_aux_clk_src", .parent_data = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk), @@ -1731,7 +1766,7 @@ static struct clk_branch gcc_pcie0_aux_clk = { .clkr = { .enable_reg = 0x28034, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie0_aux_clk", .parent_hws = (const struct clk_hw *[]) { &pcie_aux_clk_src.clkr.hw @@ -1748,7 +1783,7 @@ static struct clk_branch gcc_pcie1_aux_clk = { .clkr = { .enable_reg = 0x29034, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie1_aux_clk", .parent_hws = (const struct clk_hw *[]) { &pcie_aux_clk_src.clkr.hw @@ -1765,7 +1800,7 @@ static struct clk_branch gcc_pcie2_aux_clk = { .clkr = { .enable_reg = 0x2a034, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie2_aux_clk", .parent_hws = (const struct clk_hw *[]) { &pcie_aux_clk_src.clkr.hw @@ -1782,7 +1817,7 @@ static struct clk_branch gcc_pcie3_aux_clk = { .clkr = { .enable_reg = 0x2b034, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie3_aux_clk", .parent_hws = (const struct clk_hw *[]) { &pcie_aux_clk_src.clkr.hw @@ -1805,7 +1840,7 @@ static struct clk_rcg2 usb0_aux_clk_src = { .mnd_width = 16, .hid_width = 5, .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "usb0_aux_clk_src", .parent_data = gcc_xo_gpll0_core_pi_sleep_clk, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk), @@ -1818,7 +1853,7 @@ static struct clk_branch gcc_usb0_aux_clk = { .clkr = { .enable_reg = 0x2c048, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb0_aux_clk", .parent_hws = (const struct clk_hw *[]) { &usb0_aux_clk_src.clkr.hw @@ -1842,7 +1877,7 @@ static struct clk_rcg2 usb0_master_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "usb0_master_clk_src", .parent_data = gcc_xo_gpll0_out_main_div2_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0), @@ -1855,7 +1890,7 @@ static struct clk_branch gcc_usb0_master_clk = { .clkr = { .enable_reg = 0x2c044, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb0_master_clk", .parent_hws = (const struct clk_hw *[]) { &usb0_master_clk_src.clkr.hw @@ -1872,7 +1907,7 @@ static struct clk_branch gcc_snoc_usb_clk = { .clkr = { .enable_reg = 0x2e058, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_snoc_usb_clk", .parent_hws = (const struct clk_hw *[]) { &usb0_master_clk_src.clkr.hw @@ -1889,7 +1924,7 @@ static struct clk_branch gcc_anoc_usb_axi_clk = { .clkr = { .enable_reg = 0x2e084, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_anoc_usb_axi_clk", .parent_hws = (const struct clk_hw *[]) { &usb0_master_clk_src.clkr.hw @@ -1913,7 +1948,7 @@ static struct clk_rcg2 usb0_mock_utmi_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "usb0_mock_utmi_clk_src", .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2), @@ -1925,7 +1960,7 @@ static struct clk_regmap_div usb0_mock_utmi_div_clk_src = { .reg = 0x2c040, .shift = 0, .width = 2, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "usb0_mock_utmi_div_clk_src", .parent_data = &(const struct clk_parent_data) { .hw = &usb0_mock_utmi_clk_src.clkr.hw, @@ -1941,7 +1976,7 @@ static struct clk_branch gcc_usb0_mock_utmi_clk = { .clkr = { .enable_reg = 0x2c04c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb0_mock_utmi_clk", .parent_hws = (const struct clk_hw *[]) { &usb0_mock_utmi_div_clk_src.clkr.hw @@ -1959,7 +1994,7 @@ static struct clk_regmap_mux usb0_pipe_clk_src = { .width = 2, .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map, .clkr = { - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "usb0_pipe_clk_src", .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo, .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo), @@ -1988,7 +2023,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "sdcc1_apps_clk_src", .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2), @@ -2001,7 +2036,7 @@ static struct clk_branch gcc_sdcc1_apps_clk = { .clkr = { .enable_reg = 0x3302c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc1_apps_clk", .parent_hws = (const struct clk_hw *[]) { &sdcc1_apps_clk_src.clkr.hw @@ -2024,7 +2059,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll4_gpll0_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "sdcc1_ice_core_clk_src", .parent_data = gcc_xo_gpll0_gpll4_gpll0_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_div2), @@ -2037,7 +2072,7 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = { .clkr = { .enable_reg = 0x33030, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc1_ice_core_clk", .parent_hws = (const struct clk_hw *[]) { &sdcc1_ice_core_clk_src.clkr.hw @@ -2062,7 +2097,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = { .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "pcnoc_bfdcd_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -2071,12 +2106,44 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = { }, }; +static struct clk_branch gcc_crypto_axi_clk = { + .halt_reg = 0x16010, + .clkr = { + .enable_reg = 0x16010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_crypto_axi_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_ahb_clk = { + .halt_reg = 0x16014, + .clkr = { + .enable_reg = 0x16014, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_crypto_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_nsscfg_clk = { .halt_reg = 0x1702c, .clkr = { .enable_reg = 0x1702c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_nsscfg_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2093,7 +2160,7 @@ static struct clk_branch gcc_nssnoc_nsscc_clk = { .clkr = { .enable_reg = 0x17030, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_nssnoc_nsscc_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2110,7 +2177,7 @@ static struct clk_branch gcc_nsscc_clk = { .clkr = { .enable_reg = 0x17034, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_nsscc_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2127,7 +2194,7 @@ static struct clk_branch gcc_nssnoc_pcnoc_1_clk = { .clkr = { .enable_reg = 0x17080, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_nssnoc_pcnoc_1_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2144,7 +2211,7 @@ static struct clk_branch gcc_qdss_dap_ahb_clk = { .clkr = { .enable_reg = 0x2d064, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_dap_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2161,7 +2228,7 @@ static struct clk_branch gcc_qdss_cfg_ahb_clk = { .clkr = { .enable_reg = 0x2d068, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_cfg_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2178,7 +2245,7 @@ static struct clk_branch gcc_qpic_ahb_clk = { .clkr = { .enable_reg = 0x32010, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qpic_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2195,7 +2262,7 @@ static struct clk_branch gcc_qpic_clk = { .clkr = { .enable_reg = 0x32014, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qpic_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2213,7 +2280,7 @@ static struct clk_branch gcc_blsp1_ahb_clk = { .clkr = { .enable_reg = 0x0b004, .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_blsp1_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2230,7 +2297,7 @@ static struct clk_branch gcc_mdio_ahb_clk = { .clkr = { .enable_reg = 0x17040, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_mdio_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2248,7 +2315,7 @@ static struct clk_branch gcc_prng_ahb_clk = { .clkr = { .enable_reg = 0x0b004, .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_prng_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2265,7 +2332,7 @@ static struct clk_branch gcc_uniphy0_ahb_clk = { .clkr = { .enable_reg = 0x1704c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_uniphy0_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2282,7 +2349,7 @@ static struct clk_branch gcc_uniphy1_ahb_clk = { .clkr = { .enable_reg = 0x1705c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_uniphy1_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2299,7 +2366,7 @@ static struct clk_branch gcc_uniphy2_ahb_clk = { .clkr = { .enable_reg = 0x1706c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_uniphy2_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2316,7 +2383,7 @@ static struct clk_branch gcc_cmn_12gpll_ahb_clk = { .clkr = { .enable_reg = 0x3a004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_cmn_12gpll_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2333,7 +2400,7 @@ static struct clk_branch gcc_cmn_12gpll_apu_clk = { .clkr = { .enable_reg = 0x3a00c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_cmn_12gpll_apu_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2350,7 +2417,7 @@ static struct clk_branch gcc_pcie0_ahb_clk = { .clkr = { .enable_reg = 0x28030, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie0_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2367,7 +2434,7 @@ static struct clk_branch gcc_pcie1_ahb_clk = { .clkr = { .enable_reg = 0x29030, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie1_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2384,7 +2451,7 @@ static struct clk_branch gcc_pcie2_ahb_clk = { .clkr = { .enable_reg = 0x2a030, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie2_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2401,7 +2468,7 @@ static struct clk_branch gcc_pcie3_ahb_clk = { .clkr = { .enable_reg = 0x2b030, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie3_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2418,7 +2485,7 @@ static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = { .clkr = { .enable_reg = 0x2c05c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb0_phy_cfg_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2435,7 +2502,7 @@ static struct clk_branch gcc_sdcc1_ahb_clk = { .clkr = { .enable_reg = 0x33034, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc1_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &pcnoc_bfdcd_clk_src.clkr.hw @@ -2460,7 +2527,7 @@ static struct clk_rcg2 system_noc_bfdcd_clk_src = { .freq_tbl = ftbl_system_noc_bfdcd_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll4_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "system_noc_bfdcd_clk_src", .parent_data = gcc_xo_gpll0_gpll4, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), @@ -2475,7 +2542,7 @@ static struct clk_branch gcc_q6ss_boot_clk = { .clkr = { .enable_reg = 0x25080, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_q6ss_boot_clk", .parent_hws = (const struct clk_hw *[]) { &system_noc_bfdcd_clk_src.clkr.hw @@ -2492,7 +2559,7 @@ static struct clk_branch gcc_nssnoc_snoc_clk = { .clkr = { .enable_reg = 0x17028, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_nssnoc_snoc_clk", .parent_hws = (const struct clk_hw *[]) { &system_noc_bfdcd_clk_src.clkr.hw @@ -2509,7 +2576,7 @@ static struct clk_branch gcc_nssnoc_snoc_1_clk = { .clkr = { .enable_reg = 0x1707c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_nssnoc_snoc_1_clk", .parent_hws = (const struct clk_hw *[]) { &system_noc_bfdcd_clk_src.clkr.hw @@ -2526,7 +2593,7 @@ static struct clk_branch gcc_qdss_etr_usb_clk = { .clkr = { .enable_reg = 0x2d060, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_etr_usb_clk", .parent_hws = (const struct clk_hw *[]) { &system_noc_bfdcd_clk_src.clkr.hw @@ -2549,7 +2616,7 @@ static struct clk_rcg2 wcss_ahb_clk_src = { .freq_tbl = ftbl_wcss_ahb_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "wcss_ahb_clk_src", .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), @@ -2562,7 +2629,7 @@ static struct clk_branch gcc_q6_ahb_clk = { .clkr = { .enable_reg = 0x25014, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_q6_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &wcss_ahb_clk_src.clkr.hw @@ -2579,7 +2646,7 @@ static struct clk_branch gcc_q6_ahb_s_clk = { .clkr = { .enable_reg = 0x25018, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_q6_ahb_s_clk", .parent_hws = (const struct clk_hw *[]) { &wcss_ahb_clk_src.clkr.hw @@ -2596,7 +2663,7 @@ static struct clk_branch gcc_wcss_ecahb_clk = { .clkr = { .enable_reg = 0x25058, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_wcss_ecahb_clk", .parent_hws = (const struct clk_hw *[]) { &wcss_ahb_clk_src.clkr.hw @@ -2613,7 +2680,7 @@ static struct clk_branch gcc_wcss_acmt_clk = { .clkr = { .enable_reg = 0x2505c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_wcss_acmt_clk", .parent_hws = (const struct clk_hw *[]) { &wcss_ahb_clk_src.clkr.hw @@ -2630,7 +2697,7 @@ static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { .clkr = { .enable_reg = 0x2e030, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_sys_noc_wcss_ahb_clk", .parent_hws = (const struct clk_hw *[]) { &wcss_ahb_clk_src.clkr.hw @@ -2654,7 +2721,7 @@ static struct clk_rcg2 wcss_axi_m_clk_src = { .freq_tbl = ftbl_wcss_axi_m_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "wcss_axi_m_clk_src", .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), @@ -2667,7 +2734,7 @@ static struct clk_branch gcc_anoc_wcss_axi_m_clk = { .clkr = { .enable_reg = 0x2e0a8, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_anoc_wcss_axi_m_clk", .parent_hws = (const struct clk_hw *[]) { &wcss_axi_m_clk_src.clkr.hw @@ -2689,7 +2756,7 @@ static struct clk_rcg2 qdss_at_clk_src = { .freq_tbl = ftbl_qdss_at_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "qdss_at_clk_src", .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2), @@ -2702,7 +2769,7 @@ static struct clk_branch gcc_q6ss_atbm_clk = { .clkr = { .enable_reg = 0x2501c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_q6ss_atbm_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_at_clk_src.clkr.hw @@ -2719,7 +2786,7 @@ static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { .clkr = { .enable_reg = 0x2503c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_wcss_dbg_ifc_atb_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_at_clk_src.clkr.hw @@ -2736,7 +2803,7 @@ static struct clk_branch gcc_nssnoc_atb_clk = { .clkr = { .enable_reg = 0x17014, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_nssnoc_atb_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_at_clk_src.clkr.hw @@ -2753,7 +2820,7 @@ static struct clk_branch gcc_qdss_at_clk = { .clkr = { .enable_reg = 0x2d038, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_at_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_at_clk_src.clkr.hw @@ -2770,7 +2837,7 @@ static struct clk_branch gcc_sys_noc_at_clk = { .clkr = { .enable_reg = 0x2e038, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_sys_noc_at_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_at_clk_src.clkr.hw @@ -2787,7 +2854,7 @@ static struct clk_branch gcc_pcnoc_at_clk = { .clkr = { .enable_reg = 0x31024, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcnoc_at_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_at_clk_src.clkr.hw @@ -2802,7 +2869,7 @@ static struct clk_branch gcc_pcnoc_at_clk = { static struct clk_fixed_factor gcc_eud_at_div_clk_src = { .mult = 1, .div = 6, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_eud_at_div_clk_src", .parent_hws = (const struct clk_hw *[]) { &qdss_at_clk_src.clkr.hw @@ -2818,7 +2885,7 @@ static struct clk_branch gcc_usb0_eud_at_clk = { .clkr = { .enable_reg = 0x30004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb0_eud_at_clk", .parent_hws = (const struct clk_hw *[]) { &gcc_eud_at_div_clk_src.hw @@ -2835,7 +2902,7 @@ static struct clk_branch gcc_qdss_eud_at_clk = { .clkr = { .enable_reg = 0x2d06c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_eud_at_clk", .parent_hws = (const struct clk_hw *[]) { &gcc_eud_at_div_clk_src.hw @@ -2858,7 +2925,7 @@ static struct clk_rcg2 qdss_stm_clk_src = { .freq_tbl = ftbl_qdss_stm_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "qdss_stm_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), @@ -2871,7 +2938,7 @@ static struct clk_branch gcc_qdss_stm_clk = { .clkr = { .enable_reg = 0x2d03c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_stm_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_stm_clk_src.clkr.hw @@ -2888,7 +2955,7 @@ static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = { .clkr = { .enable_reg = 0x2e034, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_sys_noc_qdss_stm_axi_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_stm_clk_src.clkr.hw @@ -2910,7 +2977,7 @@ static struct clk_rcg2 qdss_traceclkin_clk_src = { .freq_tbl = ftbl_qdss_traceclkin_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "qdss_traceclkin_clk_src", .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2), @@ -2923,7 +2990,7 @@ static struct clk_branch gcc_qdss_traceclkin_clk = { .clkr = { .enable_reg = 0x2d040, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_traceclkin_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_traceclkin_clk_src.clkr.hw @@ -2945,7 +3012,7 @@ static struct clk_rcg2 qdss_tsctr_clk_src = { .freq_tbl = ftbl_qdss_tsctr_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "qdss_tsctr_clk_src", .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2, .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2), @@ -2956,7 +3023,7 @@ static struct clk_rcg2 qdss_tsctr_clk_src = { static struct clk_fixed_factor qdss_tsctr_div2_clk_src = { .mult = 1, .div = 2, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "qdss_tsctr_div2_clk_src", .parent_hws = (const struct clk_hw *[]) { &qdss_tsctr_clk_src.clkr.hw @@ -2972,7 +3039,7 @@ static struct clk_branch gcc_q6_tsctr_1to2_clk = { .clkr = { .enable_reg = 0x25020, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_q6_tsctr_1to2_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_tsctr_div2_clk_src.hw @@ -2989,7 +3056,7 @@ static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { .clkr = { .enable_reg = 0x25040, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_wcss_dbg_ifc_nts_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_tsctr_div2_clk_src.hw @@ -3006,7 +3073,7 @@ static struct clk_branch gcc_qdss_tsctr_div2_clk = { .clkr = { .enable_reg = 0x2d044, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_tsctr_div2_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_tsctr_div2_clk_src.hw @@ -3029,7 +3096,7 @@ static struct clk_rcg2 uniphy_sys_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "uniphy_sys_clk_src", .parent_data = gcc_xo_data, .num_parents = ARRAY_SIZE(gcc_xo_data), @@ -3043,7 +3110,7 @@ static struct clk_rcg2 nss_ts_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "nss_ts_clk_src", .parent_data = gcc_xo_data, .num_parents = ARRAY_SIZE(gcc_xo_data), @@ -3056,7 +3123,7 @@ static struct clk_branch gcc_qdss_ts_clk = { .clkr = { .enable_reg = 0x2d078, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_ts_clk", .parent_hws = (const struct clk_hw *[]) { &nss_ts_clk_src.clkr.hw @@ -3071,7 +3138,7 @@ static struct clk_branch gcc_qdss_ts_clk = { static struct clk_fixed_factor qdss_dap_sync_clk_src = { .mult = 1, .div = 4, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "qdss_dap_sync_clk_src", .parent_hws = (const struct clk_hw *[]) { &qdss_tsctr_clk_src.clkr.hw @@ -3086,7 +3153,7 @@ static struct clk_branch gcc_qdss_tsctr_div4_clk = { .clkr = { .enable_reg = 0x2d04c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_tsctr_div4_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_dap_sync_clk_src.hw @@ -3101,7 +3168,7 @@ static struct clk_branch gcc_qdss_tsctr_div4_clk = { static struct clk_fixed_factor qdss_tsctr_div8_clk_src = { .mult = 1, .div = 8, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "qdss_tsctr_div8_clk_src", .parent_hws = (const struct clk_hw *[]) { &qdss_tsctr_clk_src.clkr.hw @@ -3116,7 +3183,7 @@ static struct clk_branch gcc_nss_ts_clk = { .clkr = { .enable_reg = 0x17018, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_nss_ts_clk", .parent_hws = (const struct clk_hw *[]) { &nss_ts_clk_src.clkr.hw @@ -3133,7 +3200,7 @@ static struct clk_branch gcc_qdss_tsctr_div8_clk = { .clkr = { .enable_reg = 0x2d050, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_tsctr_div8_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_tsctr_div8_clk_src.hw @@ -3148,7 +3215,7 @@ static struct clk_branch gcc_qdss_tsctr_div8_clk = { static struct clk_fixed_factor qdss_tsctr_div16_clk_src = { .mult = 1, .div = 16, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "qdss_tsctr_div16_clk_src", .parent_hws = (const struct clk_hw *[]) { &qdss_tsctr_clk_src.clkr.hw @@ -3163,7 +3230,7 @@ static struct clk_branch gcc_qdss_tsctr_div16_clk = { .clkr = { .enable_reg = 0x2d054, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_tsctr_div16_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_tsctr_div16_clk_src.hw @@ -3180,7 +3247,7 @@ static struct clk_branch gcc_q6ss_pclkdbg_clk = { .clkr = { .enable_reg = 0x25024, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_q6ss_pclkdbg_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_dap_sync_clk_src.hw @@ -3197,7 +3264,7 @@ static struct clk_branch gcc_q6ss_trig_clk = { .clkr = { .enable_reg = 0x25068, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_q6ss_trig_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_dap_sync_clk_src.hw @@ -3214,7 +3281,7 @@ static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = { .clkr = { .enable_reg = 0x25038, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_wcss_dbg_ifc_apb_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_dap_sync_clk_src.hw @@ -3231,7 +3298,7 @@ static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { .clkr = { .enable_reg = 0x25044, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_wcss_dbg_ifc_dapbus_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_dap_sync_clk_src.hw @@ -3248,7 +3315,7 @@ static struct clk_branch gcc_qdss_dap_clk = { .clkr = { .enable_reg = 0x2d058, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_dap_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_dap_sync_clk_src.hw @@ -3265,7 +3332,7 @@ static struct clk_branch gcc_qdss_apb2jtag_clk = { .clkr = { .enable_reg = 0x2d05c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_apb2jtag_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_dap_sync_clk_src.hw @@ -3280,7 +3347,7 @@ static struct clk_branch gcc_qdss_apb2jtag_clk = { static struct clk_fixed_factor qdss_tsctr_div3_clk_src = { .mult = 1, .div = 3, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "qdss_tsctr_div3_clk_src", .parent_hws = (const struct clk_hw *[]) { &qdss_tsctr_clk_src.clkr.hw @@ -3295,7 +3362,7 @@ static struct clk_branch gcc_qdss_tsctr_div3_clk = { .clkr = { .enable_reg = 0x2d048, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_qdss_tsctr_div3_clk", .parent_hws = (const struct clk_hw *[]) { &qdss_tsctr_div3_clk_src.hw @@ -3321,7 +3388,7 @@ static struct clk_rcg2 qpic_io_macro_clk_src = { .freq_tbl = ftbl_qpic_io_macro_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "qpic_io_macro_clk_src", .parent_data = gcc_xo_gpll0_gpll2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), @@ -3334,7 +3401,7 @@ static struct clk_branch gcc_qpic_io_macro_clk = { .clkr = { .enable_reg = 0x3200c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data){ .name = "gcc_qpic_io_macro_clk", .parent_hws = (const struct clk_hw *[]){ &qpic_io_macro_clk_src.clkr.hw @@ -3356,7 +3423,7 @@ static struct clk_rcg2 q6_axi_clk_src = { .freq_tbl = ftbl_q6_axi_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "q6_axi_clk_src", .parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep), @@ -3369,7 +3436,7 @@ static struct clk_branch gcc_q6_axim_clk = { .clkr = { .enable_reg = 0x2500c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_q6_axim_clk", .parent_hws = (const struct clk_hw *[]) { &q6_axi_clk_src.clkr.hw @@ -3387,7 +3454,7 @@ static struct clk_branch gcc_wcss_q6_tbu_clk = { .clkr = { .enable_reg = 0xb00c, .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_wcss_q6_tbu_clk", .parent_hws = (const struct clk_hw *[]) { &q6_axi_clk_src.clkr.hw @@ -3404,7 +3471,7 @@ static struct clk_branch gcc_mem_noc_q6_axi_clk = { .clkr = { .enable_reg = 0x19010, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_mem_noc_q6_axi_clk", .parent_hws = (const struct clk_hw *[]) { &q6_axi_clk_src.clkr.hw @@ -3433,7 +3500,7 @@ static struct clk_rcg2 q6_axim2_clk_src = { .freq_tbl = ftbl_q6_axim2_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "q6_axim2_clk_src", .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk), @@ -3451,7 +3518,7 @@ static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = { .freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "nssnoc_memnoc_bfdcd_clk_src", .parent_data = gcc_xo_gpll0_gpll0_aux_gpll2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2), @@ -3464,7 +3531,7 @@ static struct clk_branch gcc_nssnoc_memnoc_clk = { .clkr = { .enable_reg = 0x17024, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_nssnoc_memnoc_clk", .parent_hws = (const struct clk_hw *[]) { &nssnoc_memnoc_bfdcd_clk_src.clkr.hw @@ -3481,7 +3548,7 @@ static struct clk_branch gcc_nssnoc_mem_noc_1_clk = { .clkr = { .enable_reg = 0x17084, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_nssnoc_mem_noc_1_clk", .parent_hws = (const struct clk_hw *[]) { &nssnoc_memnoc_bfdcd_clk_src.clkr.hw @@ -3498,7 +3565,7 @@ static struct clk_branch gcc_nss_tbu_clk = { .clkr = { .enable_reg = 0xb00c, .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_nss_tbu_clk", .parent_hws = (const struct clk_hw *[]) { &nssnoc_memnoc_bfdcd_clk_src.clkr.hw @@ -3515,7 +3582,7 @@ static struct clk_branch gcc_mem_noc_nssnoc_clk = { .clkr = { .enable_reg = 0x19014, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_mem_noc_nssnoc_clk", .parent_hws = (const struct clk_hw *[]) { &nssnoc_memnoc_bfdcd_clk_src.clkr.hw @@ -3537,7 +3604,7 @@ static struct clk_rcg2 lpass_axim_clk_src = { .freq_tbl = ftbl_lpass_axim_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "lpass_axim_clk_src", .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), @@ -3550,7 +3617,7 @@ static struct clk_rcg2 lpass_sway_clk_src = { .freq_tbl = ftbl_lpass_axim_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "lpass_sway_clk_src", .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), @@ -3569,7 +3636,7 @@ static struct clk_rcg2 adss_pwm_clk_src = { .freq_tbl = ftbl_adss_pwm_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "adss_pwm_clk_src", .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), @@ -3582,7 +3649,7 @@ static struct clk_branch gcc_adss_pwm_clk = { .clkr = { .enable_reg = 0x1c00c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_adss_pwm_clk", .parent_hws = (const struct clk_hw *[]) { &adss_pwm_clk_src.clkr.hw @@ -3605,7 +3672,7 @@ static struct clk_rcg2 gp1_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "gp1_clk_src", .parent_data = gcc_xo_gpll0_gpll0_sleep_clk, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk), @@ -3618,7 +3685,7 @@ static struct clk_rcg2 gp2_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "gp2_clk_src", .parent_data = gcc_xo_gpll0_gpll0_sleep_clk, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk), @@ -3631,7 +3698,7 @@ static struct clk_rcg2 gp3_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "gp3_clk_src", .parent_data = gcc_xo_gpll0_gpll0_sleep_clk, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk), @@ -3644,7 +3711,7 @@ static struct clk_branch gcc_xo_clk_src = { .clkr = { .enable_reg = 0x34004, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_xo_clk_src", .parent_data = gcc_xo_data, .num_parents = ARRAY_SIZE(gcc_xo_data), @@ -3659,7 +3726,7 @@ static struct clk_branch gcc_nssnoc_xo_dcd_clk = { .clkr = { .enable_reg = 0x17074, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_nssnoc_xo_dcd_clk", .parent_hws = (const struct clk_hw *[]) { &gcc_xo_clk_src.clkr.hw @@ -3676,7 +3743,7 @@ static struct clk_branch gcc_xo_clk = { .clkr = { .enable_reg = 0x34018, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_xo_clk", .parent_hws = (const struct clk_hw *[]) { &gcc_xo_clk_src.clkr.hw @@ -3693,7 +3760,7 @@ static struct clk_branch gcc_uniphy0_sys_clk = { .clkr = { .enable_reg = 0x17048, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_uniphy0_sys_clk", .parent_hws = (const struct clk_hw *[]) { &uniphy_sys_clk_src.clkr.hw @@ -3710,7 +3777,7 @@ static struct clk_branch gcc_uniphy1_sys_clk = { .clkr = { .enable_reg = 0x17058, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_uniphy1_sys_clk", .parent_hws = (const struct clk_hw *[]) { &uniphy_sys_clk_src.clkr.hw @@ -3727,7 +3794,7 @@ static struct clk_branch gcc_uniphy2_sys_clk = { .clkr = { .enable_reg = 0x17068, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_uniphy2_sys_clk", .parent_hws = (const struct clk_hw *[]) { &uniphy_sys_clk_src.clkr.hw @@ -3744,7 +3811,7 @@ static struct clk_branch gcc_cmn_12gpll_sys_clk = { .clkr = { .enable_reg = 0x3a008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_cmn_12gpll_sys_clk", .parent_hws = (const struct clk_hw *[]) { &uniphy_sys_clk_src.clkr.hw @@ -3759,7 +3826,7 @@ static struct clk_branch gcc_cmn_12gpll_sys_clk = { static struct clk_fixed_factor gcc_xo_div4_clk_src = { .mult = 1, .div = 4, - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_xo_div4_clk_src", .parent_hws = (const struct clk_hw *[]) { &gcc_xo_clk_src.clkr.hw @@ -3775,7 +3842,7 @@ static struct clk_branch gcc_nssnoc_qosgen_ref_clk = { .clkr = { .enable_reg = 0x1701c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_nssnoc_qosgen_ref_clk", .parent_hws = (const struct clk_hw *[]) { &gcc_xo_div4_clk_src.hw @@ -3792,7 +3859,7 @@ static struct clk_branch gcc_nssnoc_timeout_ref_clk = { .clkr = { .enable_reg = 0x17020, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_nssnoc_timeout_ref_clk", .parent_hws = (const struct clk_hw *[]) { &gcc_xo_div4_clk_src.hw @@ -3809,7 +3876,7 @@ static struct clk_branch gcc_xo_div4_clk = { .clkr = { .enable_reg = 0x3401c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "gcc_xo_div4_clk", .parent_hws = (const struct clk_hw *[]) { &gcc_xo_div4_clk_src.hw @@ -3880,6 +3947,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, + [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, + [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, + [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, + [GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr, [PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr, [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr, [PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr, @@ -4063,6 +4134,7 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = { [GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 }, [GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 }, [GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 }, + [GCC_CRYPTO_BCR] = { 0x16000, 0 }, [GCC_DCC_BCR] = { 0x35000, 0 }, [GCC_DDRSS_BCR] = { 0x11000, 0 }, [GCC_IMEM_BCR] = { 0x0e000, 0 }, diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c index 096deff2ba25..48995e50c6bd 100644 --- a/drivers/clk/qcom/gcc-qcm2290.c +++ b/drivers/clk/qcom/gcc-qcm2290.c @@ -650,7 +650,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .name = "gcc_usb30_prim_mock_utmi_clk_src", .parent_data = gcc_parents_0, .num_parents = ARRAY_SIZE(gcc_parents_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -686,7 +686,7 @@ static struct clk_rcg2 gcc_camss_axi_clk_src = { .name = "gcc_camss_axi_clk_src", .parent_data = gcc_parents_4, .num_parents = ARRAY_SIZE(gcc_parents_4), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -706,7 +706,7 @@ static struct clk_rcg2 gcc_camss_cci_clk_src = { .name = "gcc_camss_cci_clk_src", .parent_data = gcc_parents_9, .num_parents = ARRAY_SIZE(gcc_parents_9), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -728,7 +728,7 @@ static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { .name = "gcc_camss_csi0phytimer_clk_src", .parent_data = gcc_parents_5, .num_parents = ARRAY_SIZE(gcc_parents_5), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -742,7 +742,7 @@ static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { .name = "gcc_camss_csi1phytimer_clk_src", .parent_data = gcc_parents_5, .num_parents = ARRAY_SIZE(gcc_parents_5), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -764,7 +764,7 @@ static struct clk_rcg2 gcc_camss_mclk0_clk_src = { .parent_data = gcc_parents_3, .num_parents = ARRAY_SIZE(gcc_parents_3), .flags = CLK_OPS_PARENT_ENABLE, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -779,7 +779,7 @@ static struct clk_rcg2 gcc_camss_mclk1_clk_src = { .parent_data = gcc_parents_3, .num_parents = ARRAY_SIZE(gcc_parents_3), .flags = CLK_OPS_PARENT_ENABLE, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -794,7 +794,7 @@ static struct clk_rcg2 gcc_camss_mclk2_clk_src = { .parent_data = gcc_parents_3, .num_parents = ARRAY_SIZE(gcc_parents_3), .flags = CLK_OPS_PARENT_ENABLE, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -809,7 +809,7 @@ static struct clk_rcg2 gcc_camss_mclk3_clk_src = { .parent_data = gcc_parents_3, .num_parents = ARRAY_SIZE(gcc_parents_3), .flags = CLK_OPS_PARENT_ENABLE, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -830,7 +830,7 @@ static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { .name = "gcc_camss_ope_ahb_clk_src", .parent_data = gcc_parents_6, .num_parents = ARRAY_SIZE(gcc_parents_6), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -854,7 +854,7 @@ static struct clk_rcg2 gcc_camss_ope_clk_src = { .parent_data = gcc_parents_6, .num_parents = ARRAY_SIZE(gcc_parents_6), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -888,7 +888,7 @@ static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { .name = "gcc_camss_tfe_0_clk_src", .parent_data = gcc_parents_7, .num_parents = ARRAY_SIZE(gcc_parents_7), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -912,7 +912,7 @@ static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { .name = "gcc_camss_tfe_0_csid_clk_src", .parent_data = gcc_parents_8, .num_parents = ARRAY_SIZE(gcc_parents_8), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -926,7 +926,7 @@ static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { .name = "gcc_camss_tfe_1_clk_src", .parent_data = gcc_parents_7, .num_parents = ARRAY_SIZE(gcc_parents_7), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -940,7 +940,7 @@ static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { .name = "gcc_camss_tfe_1_csid_clk_src", .parent_data = gcc_parents_8, .num_parents = ARRAY_SIZE(gcc_parents_8), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -963,7 +963,7 @@ static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { .parent_data = gcc_parents_10, .num_parents = ARRAY_SIZE(gcc_parents_10), .flags = CLK_OPS_PARENT_ENABLE, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -984,7 +984,7 @@ static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { .name = "gcc_camss_top_ahb_clk_src", .parent_data = gcc_parents_4, .num_parents = ARRAY_SIZE(gcc_parents_4), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1006,7 +1006,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { .name = "gcc_gp1_clk_src", .parent_data = gcc_parents_2, .num_parents = ARRAY_SIZE(gcc_parents_2), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1020,7 +1020,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { .name = "gcc_gp2_clk_src", .parent_data = gcc_parents_2, .num_parents = ARRAY_SIZE(gcc_parents_2), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1034,7 +1034,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { .name = "gcc_gp3_clk_src", .parent_data = gcc_parents_2, .num_parents = ARRAY_SIZE(gcc_parents_2), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1054,7 +1054,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { .name = "gcc_pdm2_clk_src", .parent_data = gcc_parents_0, .num_parents = ARRAY_SIZE(gcc_parents_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1082,7 +1082,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { .name = "gcc_qupv3_wrap0_s0_clk_src", .parent_data = gcc_parents_1, .num_parents = ARRAY_SIZE(gcc_parents_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { @@ -1098,7 +1098,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { .name = "gcc_qupv3_wrap0_s1_clk_src", .parent_data = gcc_parents_1, .num_parents = ARRAY_SIZE(gcc_parents_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { @@ -1114,7 +1114,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { .name = "gcc_qupv3_wrap0_s2_clk_src", .parent_data = gcc_parents_1, .num_parents = ARRAY_SIZE(gcc_parents_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { @@ -1130,7 +1130,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { .name = "gcc_qupv3_wrap0_s3_clk_src", .parent_data = gcc_parents_1, .num_parents = ARRAY_SIZE(gcc_parents_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { @@ -1146,7 +1146,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { .name = "gcc_qupv3_wrap0_s4_clk_src", .parent_data = gcc_parents_1, .num_parents = ARRAY_SIZE(gcc_parents_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { @@ -1162,7 +1162,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { .name = "gcc_qupv3_wrap0_s5_clk_src", .parent_data = gcc_parents_1, .num_parents = ARRAY_SIZE(gcc_parents_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { @@ -1219,7 +1219,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { .name = "gcc_sdcc1_ice_core_clk_src", .parent_data = gcc_parents_0, .num_parents = ARRAY_SIZE(gcc_parents_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1266,7 +1266,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .name = "gcc_usb30_prim_master_clk_src", .parent_data = gcc_parents_0, .num_parents = ARRAY_SIZE(gcc_parents_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1280,7 +1280,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .name = "gcc_usb3_prim_phy_aux_clk_src", .parent_data = gcc_parents_13, .num_parents = ARRAY_SIZE(gcc_parents_13), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1303,7 +1303,7 @@ static struct clk_rcg2 gcc_video_venus_clk_src = { .parent_data = gcc_parents_14, .num_parents = ARRAY_SIZE(gcc_parents_14), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index 04a99dbaa57e..b90c71637814 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -9,6 +9,7 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/of_device.h> +#include <linux/pm_runtime.h> #include <linux/of.h> #include <linux/regmap.h> @@ -7421,9 +7422,19 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev) struct regmap *regmap; int ret; + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + regmap = qcom_cc_map(pdev, &gcc_sc8280xp_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } /* * Keep the clocks always-ON @@ -7445,7 +7456,10 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev) if (ret) return ret; - return qcom_cc_really_probe(pdev, &gcc_sc8280xp_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gcc_sc8280xp_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; } static const struct of_device_id gcc_sc8280xp_match_table[] = { diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c index db918c92a522..6afce8e42ede 100644 --- a/drivers/clk/qcom/gcc-sdm660.c +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -25,8 +25,6 @@ #include "reset.h" #include "gdsc.h" -#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } - enum { P_XO, P_SLEEP_CLK, diff --git a/drivers/clk/qcom/gcc-sdx75.c b/drivers/clk/qcom/gcc-sdx75.c new file mode 100644 index 000000000000..b6772abdcec5 --- /dev/null +++ b/drivers/clk/qcom/gcc-sdx75.c @@ -0,0 +1,2970 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,sdx75-gcc.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_EMAC0_SGMIIPHY_MAC_RCLK, + DT_EMAC0_SGMIIPHY_MAC_TCLK, + DT_EMAC0_SGMIIPHY_RCLK, + DT_EMAC0_SGMIIPHY_TCLK, + DT_EMAC1_SGMIIPHY_MAC_RCLK, + DT_EMAC1_SGMIIPHY_MAC_TCLK, + DT_EMAC1_SGMIIPHY_RCLK, + DT_EMAC1_SGMIIPHY_TCLK, + DT_PCIE20_PHY_AUX_CLK, + DT_PCIE_1_PIPE_CLK, + DT_PCIE_2_PIPE_CLK, + DT_PCIE_PIPE_CLK, + DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, +}; + +enum { + P_BI_TCXO, + P_EMAC0_SGMIIPHY_MAC_RCLK, + P_EMAC0_SGMIIPHY_MAC_TCLK, + P_EMAC0_SGMIIPHY_RCLK, + P_EMAC0_SGMIIPHY_TCLK, + P_EMAC1_SGMIIPHY_MAC_RCLK, + P_EMAC1_SGMIIPHY_MAC_TCLK, + P_EMAC1_SGMIIPHY_RCLK, + P_EMAC1_SGMIIPHY_TCLK, + P_GPLL0_OUT_EVEN, + P_GPLL0_OUT_MAIN, + P_GPLL4_OUT_MAIN, + P_GPLL5_OUT_MAIN, + P_GPLL6_OUT_MAIN, + P_GPLL8_OUT_MAIN, + P_PCIE20_PHY_AUX_CLK, + P_PCIE_1_PIPE_CLK, + P_PCIE_2_PIPE_CLK, + P_PCIE_PIPE_CLK, + P_SLEEP_CLK, + P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, +}; + +static struct clk_alpha_pll gpll0 = { + .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .enable_reg = 0x7d000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll0_out_even = { + .offset = 0x0, + .post_div_shift = 10, + .post_div_table = post_div_table_gpll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &gpll0.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static struct clk_alpha_pll gpll4 = { + .offset = 0x4000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .enable_reg = 0x7d000, + .enable_mask = BIT(4), + .hw.init = &(const struct clk_init_data) { + .name = "gpll4", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll5 = { + .offset = 0x5000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .enable_reg = 0x7d000, + .enable_mask = BIT(5), + .hw.init = &(const struct clk_init_data) { + .name = "gpll5", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll6 = { + .offset = 0x6000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .enable_reg = 0x7d000, + .enable_mask = BIT(6), + .hw.init = &(const struct clk_init_data) { + .name = "gpll6", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll8 = { + .offset = 0x8000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .enable_reg = 0x7d000, + .enable_mask = BIT(8), + .hw.init = &(const struct clk_init_data) { + .name = "gpll8", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct parent_map gcc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_MAIN, 2 }, + { P_GPLL5_OUT_MAIN, 5 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll4.clkr.hw }, + { .hw = &gpll5.clkr.hw }, + { .hw = &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .index = DT_SLEEP_CLK }, + { .hw = &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_5[] = { + { P_EMAC0_SGMIIPHY_RCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] = { + { .index = DT_EMAC0_SGMIIPHY_RCLK }, + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_6[] = { + { P_EMAC0_SGMIIPHY_TCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_6[] = { + { .index = DT_EMAC0_SGMIIPHY_TCLK }, + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_7[] = { + { P_EMAC0_SGMIIPHY_MAC_RCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_7[] = { + { .index = DT_EMAC0_SGMIIPHY_MAC_RCLK }, + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_8[] = { + { P_EMAC0_SGMIIPHY_MAC_TCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_8[] = { + { .index = DT_EMAC0_SGMIIPHY_MAC_TCLK }, + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_9[] = { + { P_EMAC1_SGMIIPHY_RCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_9[] = { + { .index = DT_EMAC1_SGMIIPHY_RCLK }, + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_10[] = { + { P_EMAC1_SGMIIPHY_TCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_10[] = { + { .index = DT_EMAC1_SGMIIPHY_TCLK }, + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_11[] = { + { P_EMAC1_SGMIIPHY_MAC_RCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_11[] = { + { .index = DT_EMAC1_SGMIIPHY_MAC_RCLK }, + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_12[] = { + { P_EMAC1_SGMIIPHY_MAC_TCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_12[] = { + { .index = DT_EMAC1_SGMIIPHY_MAC_TCLK }, + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_15[] = { + { P_PCIE20_PHY_AUX_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_15[] = { + { .index = DT_PCIE20_PHY_AUX_CLK }, + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_17[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL6_OUT_MAIN, 2 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_17[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll6.clkr.hw }, + { .hw = &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_18[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL8_OUT_MAIN, 2 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_18[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll8.clkr.hw }, + { .hw = &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_19[] = { + { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_19[] = { + { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK }, + { .index = DT_BI_TCXO }, +}; + +static struct clk_regmap_mux gcc_emac0_cc_sgmiiphy_rx_clk_src = { + .reg = 0x71060, + .shift = 0, + .width = 2, + .parent_map = gcc_parent_map_5, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_cc_sgmiiphy_rx_clk_src", + .parent_data = gcc_parent_data_5, + .num_parents = ARRAY_SIZE(gcc_parent_data_5), + .ops = &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_emac0_cc_sgmiiphy_tx_clk_src = { + .reg = 0x71058, + .shift = 0, + .width = 2, + .parent_map = gcc_parent_map_6, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_cc_sgmiiphy_tx_clk_src", + .parent_data = gcc_parent_data_6, + .num_parents = ARRAY_SIZE(gcc_parent_data_6), + .ops = &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_emac0_sgmiiphy_mac_rclk_src = { + .reg = 0x71098, + .shift = 0, + .width = 2, + .parent_map = gcc_parent_map_7, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_sgmiiphy_mac_rclk_src", + .parent_data = gcc_parent_data_7, + .num_parents = ARRAY_SIZE(gcc_parent_data_7), + .ops = &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_emac0_sgmiiphy_mac_tclk_src = { + .reg = 0x71094, + .shift = 0, + .width = 2, + .parent_map = gcc_parent_map_8, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_sgmiiphy_mac_tclk_src", + .parent_data = gcc_parent_data_8, + .num_parents = ARRAY_SIZE(gcc_parent_data_8), + .ops = &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_emac1_cc_sgmiiphy_rx_clk_src = { + .reg = 0x72060, + .shift = 0, + .width = 2, + .parent_map = gcc_parent_map_9, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_cc_sgmiiphy_rx_clk_src", + .parent_data = gcc_parent_data_9, + .num_parents = ARRAY_SIZE(gcc_parent_data_9), + .ops = &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_emac1_cc_sgmiiphy_tx_clk_src = { + .reg = 0x72058, + .shift = 0, + .width = 2, + .parent_map = gcc_parent_map_10, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_cc_sgmiiphy_tx_clk_src", + .parent_data = gcc_parent_data_10, + .num_parents = ARRAY_SIZE(gcc_parent_data_10), + .ops = &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_emac1_sgmiiphy_mac_rclk_src = { + .reg = 0x72098, + .shift = 0, + .width = 2, + .parent_map = gcc_parent_map_11, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_sgmiiphy_mac_rclk_src", + .parent_data = gcc_parent_data_11, + .num_parents = ARRAY_SIZE(gcc_parent_data_11), + .ops = &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_emac1_sgmiiphy_mac_tclk_src = { + .reg = 0x72094, + .shift = 0, + .width = 2, + .parent_map = gcc_parent_map_12, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_sgmiiphy_mac_tclk_src", + .parent_data = gcc_parent_data_12, + .num_parents = ARRAY_SIZE(gcc_parent_data_12), + .ops = &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { + .reg = 0x67084, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_1_pipe_clk_src", + .parent_data = &(const struct clk_parent_data) { + .index = DT_PCIE_1_PIPE_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_2_pipe_clk_src = { + .reg = 0x68050, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_2_pipe_clk_src", + .parent_data = &(const struct clk_parent_data) { + .index = DT_PCIE_2_PIPE_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_pcie_aux_clk_src = { + .reg = 0x53074, + .shift = 0, + .width = 2, + .parent_map = gcc_parent_map_15, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_aux_clk_src", + .parent_data = gcc_parent_data_15, + .num_parents = ARRAY_SIZE(gcc_parent_data_15), + .ops = &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_pipe_clk_src = { + .reg = 0x53058, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_pipe_clk_src", + .parent_data = &(const struct clk_parent_data) { + .index = DT_PCIE_PIPE_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_usb3_phy_pipe_clk_src = { + .reg = 0x27070, + .shift = 0, + .width = 2, + .parent_map = gcc_parent_map_19, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb3_phy_pipe_clk_src", + .parent_data = gcc_parent_data_19, + .num_parents = ARRAY_SIZE(gcc_parent_data_19), + .ops = &clk_regmap_mux_closest_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_gcc_eee_emac0_clk_src[] = { + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_eee_emac0_clk_src = { + .cmd_rcgr = 0x710b0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_eee_emac0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_eee_emac0_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_eee_emac1_clk_src = { + .cmd_rcgr = 0x720b0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_eee_emac0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_eee_emac1_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_phy_aux_clk_src = { + .cmd_rcgr = 0x7102c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_phy_aux_clk_src", + .parent_data = gcc_parent_data_4, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = { + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(125000000, P_GPLL4_OUT_MAIN, 4, 0, 0), + F(230400000, P_GPLL5_OUT_MAIN, 3.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_ptp_clk_src = { + .cmd_rcgr = 0x7107c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_emac0_ptp_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_ptp_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = { + F(5000000, P_GPLL0_OUT_EVEN, 10, 1, 6), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(125000000, P_GPLL4_OUT_MAIN, 4, 0, 0), + F(250000000, P_GPLL4_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_rgmii_clk_src = { + .cmd_rcgr = 0x71064, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_rgmii_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_emac1_phy_aux_clk_src = { + .cmd_rcgr = 0x7202c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_phy_aux_clk_src", + .parent_data = gcc_parent_data_4, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_emac1_ptp_clk_src = { + .cmd_rcgr = 0x7207c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_emac0_ptp_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_ptp_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_emac1_rgmii_clk_src = { + .cmd_rcgr = 0x72064, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_rgmii_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src = { + .cmd_rcgr = 0x47004, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_gp1_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src = { + .cmd_rcgr = 0x48004, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_gp2_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src = { + .cmd_rcgr = 0x49004, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_gp3_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_1_aux_phy_clk_src = { + .cmd_rcgr = 0x67044, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_1_aux_phy_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_1_phy_rchng_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { + .cmd_rcgr = 0x6706c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_pcie_1_phy_rchng_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_1_phy_rchng_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_2_aux_phy_clk_src = { + .cmd_rcgr = 0x68064, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_2_aux_phy_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = { + .cmd_rcgr = 0x68038, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_pcie_1_phy_rchng_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_2_phy_rchng_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = { + .cmd_rcgr = 0x5305c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_aux_phy_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = { + .cmd_rcgr = 0x53078, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_pcie_1_phy_rchng_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_rchng_phy_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src = { + .cmd_rcgr = 0x34010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_pdm2_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm2_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), + F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { + .name = "gcc_qupv3_wrap0_s0_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { + .cmd_rcgr = 0x6c010, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { + .name = "gcc_qupv3_wrap0_s1_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { + .cmd_rcgr = 0x6c148, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { + .name = "gcc_qupv3_wrap0_s2_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { + .cmd_rcgr = 0x6c280, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { + .name = "gcc_qupv3_wrap0_s3_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { + .cmd_rcgr = 0x6c3b8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { + .name = "gcc_qupv3_wrap0_s4_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { + .cmd_rcgr = 0x6c4f0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { + .name = "gcc_qupv3_wrap0_s5_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { + .cmd_rcgr = 0x6c628, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { + .name = "gcc_qupv3_wrap0_s6_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { + .cmd_rcgr = 0x6c760, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { + .name = "gcc_qupv3_wrap0_s7_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { + .cmd_rcgr = 0x6c898, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s8_clk_src_init = { + .name = "gcc_qupv3_wrap0_s8_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s8_clk_src = { + .cmd_rcgr = 0x6c9d0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s8_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { + F(144000, P_BI_TCXO, 16, 3, 25), + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), + F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { + .cmd_rcgr = 0x6b014, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_17, + .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_sdcc1_apps_clk_src", + .parent_data = gcc_parent_data_17, + .num_parents = ARRAY_SIZE(gcc_parent_data_17), + .ops = &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(202000000, P_GPLL8_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { + .cmd_rcgr = 0x6a018, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_18, + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_sdcc2_apps_clk_src", + .parent_data = gcc_parent_data_18, + .num_parents = ARRAY_SIZE(gcc_parent_data_18), + .ops = &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = { + F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_master_clk_src = { + .cmd_rcgr = 0x27034, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_usb30_master_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_usb30_master_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = { + .cmd_rcgr = 0x2704c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_usb30_mock_utmi_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = { + F(1000000, P_BI_TCXO, 1, 5, 96), + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = { + .cmd_rcgr = 0x27074, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_usb3_phy_aux_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gcc_pcie_1_pipe_div2_clk_src = { + .reg = 0x67088, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_1_pipe_div2_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_1_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_pcie_2_pipe_div2_clk_src = { + .reg = 0x68088, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_2_pipe_div2_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_2_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb30_mock_utmi_postdiv_clk_src = { + .reg = 0x27064, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_usb30_mock_utmi_postdiv_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb30_mock_utmi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x37004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x37004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7d008, + .enable_mask = BIT(26), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_boot_rom_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_eee_emac0_clk = { + .halt_reg = 0x710ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x710ac, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_eee_emac0_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_eee_emac0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_eee_emac1_clk = { + .halt_reg = 0x720ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x720ac, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_eee_emac1_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_eee_emac1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_axi_clk = { + .halt_reg = 0x71018, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x71018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x71018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_cc_sgmiiphy_rx_clk = { + .halt_reg = 0x7105c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x7105c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_cc_sgmiiphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_cc_sgmiiphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_cc_sgmiiphy_tx_clk = { + .halt_reg = 0x71054, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x71054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_cc_sgmiiphy_tx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_cc_sgmiiphy_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_phy_aux_clk = { + .halt_reg = 0x71028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x71028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_ptp_clk = { + .halt_reg = 0x71044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x71044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_ptp_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_ptp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_rgmii_clk = { + .halt_reg = 0x71050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x71050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_rgmii_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_rgmii_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_rpcs_rx_clk = { + .halt_reg = 0x710a0, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x710a0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_rpcs_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_sgmiiphy_mac_rclk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_rpcs_tx_clk = { + .halt_reg = 0x7109c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x7109c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_rpcs_tx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_sgmiiphy_mac_tclk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_slv_ahb_clk = { + .halt_reg = 0x71024, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x71024, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x71024, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_slv_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_xgxs_rx_clk = { + .halt_reg = 0x710a8, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x710a8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_xgxs_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_sgmiiphy_mac_rclk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_xgxs_tx_clk = { + .halt_reg = 0x710a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x710a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac0_xgxs_tx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac0_sgmiiphy_mac_tclk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_axi_clk = { + .halt_reg = 0x72018, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x72018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x72018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_cc_sgmiiphy_rx_clk = { + .halt_reg = 0x7205c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x7205c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_cc_sgmiiphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_cc_sgmiiphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_cc_sgmiiphy_tx_clk = { + .halt_reg = 0x72054, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x72054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_cc_sgmiiphy_tx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_cc_sgmiiphy_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_phy_aux_clk = { + .halt_reg = 0x72028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x72028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_ptp_clk = { + .halt_reg = 0x72044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x72044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_ptp_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_ptp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_rgmii_clk = { + .halt_reg = 0x72050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x72050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_rgmii_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_rgmii_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_rpcs_rx_clk = { + .halt_reg = 0x720a0, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x720a0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_rpcs_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_sgmiiphy_mac_rclk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_rpcs_tx_clk = { + .halt_reg = 0x7209c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x7209c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_rpcs_tx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_sgmiiphy_mac_tclk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_slv_ahb_clk = { + .halt_reg = 0x72024, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x72024, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x72024, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_slv_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_xgxs_rx_clk = { + .halt_reg = 0x720a8, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x720a8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_xgxs_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_sgmiiphy_mac_rclk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_xgxs_tx_clk = { + .halt_reg = 0x720a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x720a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac1_xgxs_tx_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_emac1_sgmiiphy_mac_tclk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac_0_clkref_en = { + .halt_reg = 0x98108, + .halt_check = BRANCH_HALT_ENABLE, + .clkr = { + .enable_reg = 0x98108, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac_0_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac_1_clkref_en = { + .halt_reg = 0x9810c, + .halt_check = BRANCH_HALT_ENABLE, + .clkr = { + .enable_reg = 0x9810c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_emac_1_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk = { + .halt_reg = 0x47000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x47000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_gp1_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk = { + .halt_reg = 0x48000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x48000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_gp2_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk = { + .halt_reg = 0x49000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x49000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_gp3_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_gp3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_clkref_en = { + .halt_reg = 0x98004, + .halt_check = BRANCH_HALT_ENABLE, + .clkr = { + .enable_reg = 0x98004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_0_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_aux_clk = { + .halt_reg = 0x67038, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(22), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_1_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_1_aux_phy_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { + .halt_reg = 0x67034, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x67034, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(21), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_1_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_clkref_en = { + .halt_reg = 0x98114, + .halt_check = BRANCH_HALT_ENABLE, + .clkr = { + .enable_reg = 0x98114, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_1_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_mstr_axi_clk = { + .halt_reg = 0x67028, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(20), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_1_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_phy_rchng_clk = { + .halt_reg = 0x67068, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(24), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_1_phy_rchng_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_pipe_clk = { + .halt_reg = 0x6705c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(23), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_1_pipe_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_1_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_pipe_div2_clk = { + .halt_reg = 0x6708c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x7d020, + .enable_mask = BIT(3), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_1_pipe_div2_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_1_pipe_div2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_slv_axi_clk = { + .halt_reg = 0x6701c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(19), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_1_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { + .halt_reg = 0x67018, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(18), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_1_slv_q2a_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_aux_clk = { + .halt_reg = 0x68058, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(29), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_2_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_2_aux_phy_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { + .halt_reg = 0x68034, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x68034, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(28), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_2_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_clkref_en = { + .halt_reg = 0x98110, + .halt_check = BRANCH_HALT_ENABLE, + .clkr = { + .enable_reg = 0x98110, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_2_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_mstr_axi_clk = { + .halt_reg = 0x68028, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d008, + .enable_mask = BIT(8), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_2_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_phy_rchng_clk = { + .halt_reg = 0x68098, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(31), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_2_phy_rchng_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_2_phy_rchng_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_pipe_clk = { + .halt_reg = 0x6807c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(30), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_2_pipe_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_2_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_pipe_div2_clk = { + .halt_reg = 0x6808c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x7d020, + .enable_mask = BIT(4), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_2_pipe_div2_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_2_pipe_div2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_slv_axi_clk = { + .halt_reg = 0x6801c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(26), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_2_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = { + .halt_reg = 0x68018, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(25), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_2_slv_q2a_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_aux_clk = { + .halt_reg = 0x5303c, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0x5303c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(15), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_cfg_ahb_clk = { + .halt_reg = 0x53034, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x53034, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(13), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_mstr_axi_clk = { + .halt_reg = 0x53028, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x53028, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(12), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_pipe_clk = { + .halt_reg = 0x5304c, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0x5304c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(17), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_pipe_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_rchng_phy_clk = { + .halt_reg = 0x53038, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x53038, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(14), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_rchng_phy_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_rchng_phy_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_sleep_clk = { + .halt_reg = 0x53048, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x53048, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(16), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_sleep_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pcie_aux_phy_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_slv_axi_clk = { + .halt_reg = 0x5301c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(11), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_slv_q2a_axi_clk = { + .halt_reg = 0x53018, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x53018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7d010, + .enable_mask = BIT(10), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie_slv_q2a_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk = { + .halt_reg = 0x3400c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3400c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm2_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x34004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x34004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk = { + .halt_reg = 0x34008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x34008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm_xo4_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { + .halt_reg = 0x2d018, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d008, + .enable_mask = BIT(15), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk = { + .halt_reg = 0x2d008, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d008, + .enable_mask = BIT(14), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk = { + .halt_reg = 0x6c004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d008, + .enable_mask = BIT(16), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s0_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk = { + .halt_reg = 0x6c13c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d008, + .enable_mask = BIT(17), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s1_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk = { + .halt_reg = 0x6c274, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d008, + .enable_mask = BIT(18), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s2_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk = { + .halt_reg = 0x6c3ac, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d008, + .enable_mask = BIT(19), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s3_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk = { + .halt_reg = 0x6c4e4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d008, + .enable_mask = BIT(20), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s4_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s5_clk = { + .halt_reg = 0x6c61c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d008, + .enable_mask = BIT(21), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s5_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s6_clk = { + .halt_reg = 0x6c754, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d008, + .enable_mask = BIT(22), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s6_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s7_clk = { + .halt_reg = 0x6c88c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d008, + .enable_mask = BIT(23), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s7_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s8_clk = { + .halt_reg = 0x6c9c4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7d020, + .enable_mask = BIT(7), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap0_s8_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s8_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { + .halt_reg = 0x2d000, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2d000, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7d008, + .enable_mask = BIT(12), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap_0_m_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { + .halt_reg = 0x2d004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2d004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7d008, + .enable_mask = BIT(13), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_qupv3_wrap_0_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk = { + .halt_reg = 0x6b004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6b004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_sdcc1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk = { + .halt_reg = 0x6b008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6b008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_sdcc1_apps_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk = { + .halt_reg = 0x6a010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6a010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_sdcc2_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk = { + .halt_reg = 0x6a004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6a004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_sdcc2_apps_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_sdcc2_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb2_clkref_en = { + .halt_reg = 0x98008, + .halt_check = BRANCH_HALT_ENABLE, + .clkr = { + .enable_reg = 0x98008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb2_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_master_clk = { + .halt_reg = 0x27018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x27018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb30_master_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb30_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_mock_utmi_clk = { + .halt_reg = 0x27030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x27030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb30_mock_utmi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb30_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_mstr_axi_clk = { + .halt_reg = 0x27024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x27024, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb30_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_sleep_clk = { + .halt_reg = 0x2702c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2702c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb30_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_slv_ahb_clk = { + .halt_reg = 0x27028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x27028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb30_slv_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_phy_aux_clk = { + .halt_reg = 0x27068, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x27068, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb3_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb3_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_phy_pipe_clk = { + .halt_reg = 0x2706c, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0x2706c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x2706c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb3_phy_pipe_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb3_phy_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_clkref_en = { + .halt_reg = 0x98000, + .halt_check = BRANCH_HALT_ENABLE, + .clkr = { + .enable_reg = 0x98000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb3_prim_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { + .halt_reg = 0x29004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x29004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x29004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_usb_phy_cfg_ahb2phy_clk", + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct gdsc gcc_emac0_gdsc = { + .gdscr = 0x71004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_emac0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_emac1_gdsc = { + .gdscr = 0x72004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_emac1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_pcie_1_gdsc = { + .gdscr = 0x67004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_pcie_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_pcie_1_phy_gdsc = { + .gdscr = 0x56004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .pd = { + .name = "gcc_pcie_1_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_pcie_2_gdsc = { + .gdscr = 0x68004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_pcie_2_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_pcie_2_phy_gdsc = { + .gdscr = 0x6e004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .pd = { + .name = "gcc_pcie_2_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_pcie_gdsc = { + .gdscr = 0x53004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_pcie_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_pcie_phy_gdsc = { + .gdscr = 0x54004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .pd = { + .name = "gcc_pcie_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb30_gdsc = { + .gdscr = 0x27004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_usb30_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb3_phy_gdsc = { + .gdscr = 0x28008, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .pd = { + .name = "gcc_usb3_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *gcc_sdx75_clocks[] = { + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_EEE_EMAC0_CLK] = &gcc_eee_emac0_clk.clkr, + [GCC_EEE_EMAC0_CLK_SRC] = &gcc_eee_emac0_clk_src.clkr, + [GCC_EEE_EMAC1_CLK] = &gcc_eee_emac1_clk.clkr, + [GCC_EEE_EMAC1_CLK_SRC] = &gcc_eee_emac1_clk_src.clkr, + [GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr, + [GCC_EMAC0_CC_SGMIIPHY_RX_CLK] = &gcc_emac0_cc_sgmiiphy_rx_clk.clkr, + [GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC] = &gcc_emac0_cc_sgmiiphy_rx_clk_src.clkr, + [GCC_EMAC0_CC_SGMIIPHY_TX_CLK] = &gcc_emac0_cc_sgmiiphy_tx_clk.clkr, + [GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC] = &gcc_emac0_cc_sgmiiphy_tx_clk_src.clkr, + [GCC_EMAC0_PHY_AUX_CLK] = &gcc_emac0_phy_aux_clk.clkr, + [GCC_EMAC0_PHY_AUX_CLK_SRC] = &gcc_emac0_phy_aux_clk_src.clkr, + [GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr, + [GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr, + [GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr, + [GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr, + [GCC_EMAC0_RPCS_RX_CLK] = &gcc_emac0_rpcs_rx_clk.clkr, + [GCC_EMAC0_RPCS_TX_CLK] = &gcc_emac0_rpcs_tx_clk.clkr, + [GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC] = &gcc_emac0_sgmiiphy_mac_rclk_src.clkr, + [GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC] = &gcc_emac0_sgmiiphy_mac_tclk_src.clkr, + [GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr, + [GCC_EMAC0_XGXS_RX_CLK] = &gcc_emac0_xgxs_rx_clk.clkr, + [GCC_EMAC0_XGXS_TX_CLK] = &gcc_emac0_xgxs_tx_clk.clkr, + [GCC_EMAC1_AXI_CLK] = &gcc_emac1_axi_clk.clkr, + [GCC_EMAC1_CC_SGMIIPHY_RX_CLK] = &gcc_emac1_cc_sgmiiphy_rx_clk.clkr, + [GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC] = &gcc_emac1_cc_sgmiiphy_rx_clk_src.clkr, + [GCC_EMAC1_CC_SGMIIPHY_TX_CLK] = &gcc_emac1_cc_sgmiiphy_tx_clk.clkr, + [GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC] = &gcc_emac1_cc_sgmiiphy_tx_clk_src.clkr, + [GCC_EMAC1_PHY_AUX_CLK] = &gcc_emac1_phy_aux_clk.clkr, + [GCC_EMAC1_PHY_AUX_CLK_SRC] = &gcc_emac1_phy_aux_clk_src.clkr, + [GCC_EMAC1_PTP_CLK] = &gcc_emac1_ptp_clk.clkr, + [GCC_EMAC1_PTP_CLK_SRC] = &gcc_emac1_ptp_clk_src.clkr, + [GCC_EMAC1_RGMII_CLK] = &gcc_emac1_rgmii_clk.clkr, + [GCC_EMAC1_RGMII_CLK_SRC] = &gcc_emac1_rgmii_clk_src.clkr, + [GCC_EMAC1_RPCS_RX_CLK] = &gcc_emac1_rpcs_rx_clk.clkr, + [GCC_EMAC1_RPCS_TX_CLK] = &gcc_emac1_rpcs_tx_clk.clkr, + [GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC] = &gcc_emac1_sgmiiphy_mac_rclk_src.clkr, + [GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC] = &gcc_emac1_sgmiiphy_mac_tclk_src.clkr, + [GCC_EMAC1_SLV_AHB_CLK] = &gcc_emac1_slv_ahb_clk.clkr, + [GCC_EMAC1_XGXS_RX_CLK] = &gcc_emac1_xgxs_rx_clk.clkr, + [GCC_EMAC1_XGXS_TX_CLK] = &gcc_emac1_xgxs_tx_clk.clkr, + [GCC_EMAC_0_CLKREF_EN] = &gcc_emac_0_clkref_en.clkr, + [GCC_EMAC_1_CLKREF_EN] = &gcc_emac_1_clkref_en.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, + [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr, + [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, + [GCC_PCIE_1_AUX_PHY_CLK_SRC] = &gcc_pcie_1_aux_phy_clk_src.clkr, + [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, + [GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr, + [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, + [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, + [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, + [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, + [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, + [GCC_PCIE_1_PIPE_DIV2_CLK] = &gcc_pcie_1_pipe_div2_clk.clkr, + [GCC_PCIE_1_PIPE_DIV2_CLK_SRC] = &gcc_pcie_1_pipe_div2_clk_src.clkr, + [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, + [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, + [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr, + [GCC_PCIE_2_AUX_PHY_CLK_SRC] = &gcc_pcie_2_aux_phy_clk_src.clkr, + [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr, + [GCC_PCIE_2_CLKREF_EN] = &gcc_pcie_2_clkref_en.clkr, + [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr, + [GCC_PCIE_2_PHY_RCHNG_CLK] = &gcc_pcie_2_phy_rchng_clk.clkr, + [GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr, + [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr, + [GCC_PCIE_2_PIPE_CLK_SRC] = &gcc_pcie_2_pipe_clk_src.clkr, + [GCC_PCIE_2_PIPE_DIV2_CLK] = &gcc_pcie_2_pipe_div2_clk.clkr, + [GCC_PCIE_2_PIPE_DIV2_CLK_SRC] = &gcc_pcie_2_pipe_div2_clk_src.clkr, + [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr, + [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr, + [GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr, + [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr, + [GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr, + [GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr, + [GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr, + [GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr, + [GCC_PCIE_PIPE_CLK_SRC] = &gcc_pcie_pipe_clk_src.clkr, + [GCC_PCIE_RCHNG_PHY_CLK] = &gcc_pcie_rchng_phy_clk.clkr, + [GCC_PCIE_RCHNG_PHY_CLK_SRC] = &gcc_pcie_rchng_phy_clk_src.clkr, + [GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr, + [GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr, + [GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, + [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, + [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, + [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, + [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, + [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, + [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, + [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, + [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, + [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, + [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, + [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, + [GCC_QUPV3_WRAP0_S8_CLK] = &gcc_qupv3_wrap0_s8_clk.clkr, + [GCC_QUPV3_WRAP0_S8_CLK_SRC] = &gcc_qupv3_wrap0_s8_clk_src.clkr, + [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, + [GCC_USB2_CLKREF_EN] = &gcc_usb2_clkref_en.clkr, + [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, + [GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr, + [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, + [GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr, + [GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mock_utmi_postdiv_clk_src.clkr, + [GCC_USB30_MSTR_AXI_CLK] = &gcc_usb30_mstr_axi_clk.clkr, + [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, + [GCC_USB30_SLV_AHB_CLK] = &gcc_usb30_slv_ahb_clk.clkr, + [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, + [GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr, + [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, + [GCC_USB3_PHY_PIPE_CLK_SRC] = &gcc_usb3_phy_pipe_clk_src.clkr, + [GCC_USB3_PRIM_CLKREF_EN] = &gcc_usb3_prim_clkref_en.clkr, + [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, + [GPLL0] = &gpll0.clkr, + [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, + [GPLL4] = &gpll4.clkr, + [GPLL5] = &gpll5.clkr, + [GPLL6] = &gpll6.clkr, + [GPLL8] = &gpll8.clkr, +}; + +static struct gdsc *gcc_sdx75_gdscs[] = { + [GCC_EMAC0_GDSC] = &gcc_emac0_gdsc, + [GCC_EMAC1_GDSC] = &gcc_emac1_gdsc, + [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc, + [GCC_PCIE_1_PHY_GDSC] = &gcc_pcie_1_phy_gdsc, + [GCC_PCIE_2_GDSC] = &gcc_pcie_2_gdsc, + [GCC_PCIE_2_PHY_GDSC] = &gcc_pcie_2_phy_gdsc, + [GCC_PCIE_GDSC] = &gcc_pcie_gdsc, + [GCC_PCIE_PHY_GDSC] = &gcc_pcie_phy_gdsc, + [GCC_USB30_GDSC] = &gcc_usb30_gdsc, + [GCC_USB3_PHY_GDSC] = &gcc_usb3_phy_gdsc, +}; + +static const struct qcom_reset_map gcc_sdx75_resets[] = { + [GCC_EMAC0_BCR] = { 0x71000 }, + [GCC_EMAC0_RGMII_CLK_ARES] = { 0x71050, 2 }, + [GCC_EMAC1_BCR] = { 0x72000 }, + [GCC_EMMC_BCR] = { 0x6b000 }, + [GCC_PCIE_1_BCR] = { 0x67000 }, + [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e700 }, + [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x56120 }, + [GCC_PCIE_1_PHY_BCR] = { 0x56000 }, + [GCC_PCIE_2_BCR] = { 0x68000 }, + [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x9f700 }, + [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x6e130 }, + [GCC_PCIE_2_PHY_BCR] = { 0x6e000 }, + [GCC_PCIE_BCR] = { 0x53000 }, + [GCC_PCIE_LINK_DOWN_BCR] = { 0x87000 }, + [GCC_PCIE_NOCSR_COM_PHY_BCR] = { 0x88008 }, + [GCC_PCIE_PHY_BCR] = { 0x54000 }, + [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x88000 }, + [GCC_PCIE_PHY_COM_BCR] = { 0x88004 }, + [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x8800c }, + [GCC_QUSB2PHY_BCR] = { 0x2a000 }, + [GCC_TCSR_PCIE_BCR] = { 0x84000 }, + [GCC_USB30_BCR] = { 0x27000 }, + [GCC_USB3_PHY_BCR] = { 0x28000 }, + [GCC_USB3PHY_PHY_BCR] = { 0x28004 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x29000 }, +}; + +static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s8_clk_src), +}; + +static const struct regmap_config gcc_sdx75_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1f41f0, + .fast_io = true, +}; + +static const struct qcom_cc_desc gcc_sdx75_desc = { + .config = &gcc_sdx75_regmap_config, + .clks = gcc_sdx75_clocks, + .num_clks = ARRAY_SIZE(gcc_sdx75_clocks), + .resets = gcc_sdx75_resets, + .num_resets = ARRAY_SIZE(gcc_sdx75_resets), + .gdscs = gcc_sdx75_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_sdx75_gdscs), +}; + +static const struct of_device_id gcc_sdx75_match_table[] = { + { .compatible = "qcom,sdx75-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_sdx75_match_table); + +static int gcc_sdx75_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap = qcom_cc_map(pdev, &gcc_sdx75_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, + ARRAY_SIZE(gcc_dfs_clocks)); + if (ret) + return ret; + + /* + * Keep clocks always enabled: + * gcc_ahb_pcie_link_clk + * gcc_xo_pcie_link_clk + */ + regmap_update_bits(regmap, 0x3e004, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x3e008, BIT(0), BIT(0)); + + return qcom_cc_really_probe(pdev, &gcc_sdx75_desc, regmap); +} + +static struct platform_driver gcc_sdx75_driver = { + .probe = gcc_sdx75_probe, + .driver = { + .name = "gcc-sdx75", + .of_match_table = gcc_sdx75_match_table, + }, +}; + +static int __init gcc_sdx75_init(void) +{ + return platform_driver_register(&gcc_sdx75_driver); +} +subsys_initcall(gcc_sdx75_init); + +static void __exit gcc_sdx75_exit(void) +{ + platform_driver_unregister(&gcc_sdx75_driver); +} +module_exit(gcc_sdx75_exit); + +MODULE_DESCRIPTION("QTI GCC SDX75 Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c index 5f09aefa7fb9..033e308ff865 100644 --- a/drivers/clk/qcom/gcc-sm6115.c +++ b/drivers/clk/qcom/gcc-sm6115.c @@ -119,6 +119,8 @@ static const struct alpha_pll_config gpll10_config = { .vco_mask = GENMASK(21, 20), .main_output_mask = BIT(0), .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, + .test_ctl_hi_mask = 0x1, }; static struct clk_alpha_pll gpll10 = { @@ -170,6 +172,8 @@ static const struct alpha_pll_config gpll11_config = { .vco_val = 0x2 << 20, .vco_mask = GENMASK(21, 20), .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, + .test_ctl_hi_mask = 0x1, }; static struct clk_alpha_pll gpll11 = { @@ -362,6 +366,8 @@ static const struct alpha_pll_config gpll8_config = { .post_div_val = 0x1 << 8, .post_div_mask = GENMASK(11, 8), .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, + .test_ctl_hi_mask = 0x1, }; static struct clk_alpha_pll gpll8 = { @@ -413,6 +419,8 @@ static const struct alpha_pll_config gpll9_config = { .post_div_mask = GENMASK(9, 8), .main_output_mask = BIT(0), .config_ctl_val = 0x00004289, + .test_ctl_mask = GENMASK(31, 0), + .test_ctl_val = 0x08000000, }; static struct clk_alpha_pll gpll9 = { diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index 84764cc3db4f..75635d40a12d 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -334,6 +334,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_gp1_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk_src", .parent_data = gcc_parent_data_1, @@ -349,6 +350,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_gp1_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk_src", .parent_data = gcc_parent_data_1, @@ -364,6 +366,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_gp1_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk_src", .parent_data = gcc_parent_data_1, @@ -384,6 +387,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_2, .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_aux_clk_src", .parent_data = gcc_parent_data_2, @@ -405,6 +409,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_phy_rchng_clk_src", .parent_data = gcc_parent_data_0, @@ -420,6 +425,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_2, .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_aux_clk_src", .parent_data = gcc_parent_data_2, @@ -435,6 +441,7 @@ static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_phy_rchng_clk_src", .parent_data = gcc_parent_data_0, @@ -455,6 +462,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_pdm2_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk_src", .parent_data = gcc_parent_data_0, @@ -493,6 +501,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, }; @@ -510,6 +519,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, }; @@ -527,6 +537,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, }; @@ -544,6 +555,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, }; @@ -561,6 +573,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, }; @@ -590,6 +603,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, }; @@ -607,6 +621,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, }; @@ -624,6 +639,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, }; @@ -660,6 +676,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, }; @@ -677,6 +694,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, }; @@ -694,6 +712,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, }; @@ -711,6 +730,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, }; @@ -728,6 +748,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, }; @@ -745,6 +766,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, }; @@ -762,6 +784,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, }; @@ -779,6 +802,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, }; @@ -796,6 +820,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, }; @@ -813,6 +838,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, }; @@ -830,6 +856,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, }; @@ -847,6 +874,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, }; @@ -864,6 +892,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, }; @@ -881,6 +910,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, }; @@ -899,6 +929,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_7, .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_7, @@ -921,6 +952,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_apps_clk_src", .parent_data = gcc_parent_data_0, @@ -944,6 +976,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_axi_clk_src", .parent_data = gcc_parent_data_0, @@ -966,6 +999,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_ice_core_clk_src", .parent_data = gcc_parent_data_0, @@ -987,6 +1021,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_3, .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_phy_aux_clk_src", .parent_data = gcc_parent_data_3, @@ -1002,6 +1037,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_unipro_core_clk_src", .parent_data = gcc_parent_data_0, @@ -1025,6 +1061,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_master_clk_src", .parent_data = gcc_parent_data_0, @@ -1040,6 +1077,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_mock_utmi_clk_src", .parent_data = gcc_parent_data_0, @@ -1055,6 +1093,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_2, .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, + .hw_clk_ctrl = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_aux_clk_src", .parent_data = gcc_parent_data_2, diff --git a/drivers/clk/qcom/gpucc-sc8280xp.c b/drivers/clk/qcom/gpucc-sc8280xp.c index ea1e9505c335..8e147ee294ee 100644 --- a/drivers/clk/qcom/gpucc-sc8280xp.c +++ b/drivers/clk/qcom/gpucc-sc8280xp.c @@ -7,6 +7,7 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_runtime.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> @@ -424,10 +425,21 @@ static struct qcom_cc_desc gpu_cc_sc8280xp_desc = { static int gpu_cc_sc8280xp_probe(struct platform_device *pdev) { struct regmap *regmap; + int ret; + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; regmap = qcom_cc_map(pdev, &gpu_cc_sc8280xp_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); @@ -439,7 +451,10 @@ static int gpu_cc_sc8280xp_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0)); regmap_update_bits(regmap, 0x109c, BIT(0), BIT(0)); - return qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; } static const struct of_device_id gpu_cc_sc8280xp_match_table[] = { diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c index d3620344a009..2d863dc3d83b 100644 --- a/drivers/clk/qcom/gpucc-sm6375.c +++ b/drivers/clk/qcom/gpucc-sm6375.c @@ -7,6 +7,7 @@ #include <linux/clk-provider.h> #include <linux/module.h> #include <linux/of_device.h> +#include <linux/pm_runtime.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,sm6375-gpucc.h> @@ -434,15 +435,29 @@ MODULE_DEVICE_TABLE(of, gpucc_sm6375_match_table); static int gpucc_sm6375_probe(struct platform_device *pdev) { struct regmap *regmap; + int ret; + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; regmap = qcom_cc_map(pdev, &gpucc_sm6375_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config); clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config); - return qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver gpucc_sm6375_driver = { diff --git a/drivers/clk/qcom/gpucc-sm8450.c b/drivers/clk/qcom/gpucc-sm8450.c new file mode 100644 index 000000000000..16c0381b3087 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm8450.c @@ -0,0 +1,766 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,sm8450-gpucc.h> +#include <dt-bindings/reset/qcom,sm8450-gpucc.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static struct pll_vco lucid_evo_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +static struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x1d, + .alpha = 0xb000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static struct alpha_pll_config gpu_cc_pll1_config = { + .l = 0x34, + .alpha = 0x1555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, +}; + +static struct clk_alpha_pll gpu_cc_pll1 = { + .offset = 0x1000, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .index = DT_GPLL0_OUT_MAIN }, + { .index = DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .index = DT_GPLL0_OUT_MAIN }, + { .index = DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .index = DT_GPLL0_OUT_MAIN }, + { .index = DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_3[] = { + { .index = DT_BI_TCXO }, +}; + +static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_ff_clk_src = { + .cmd_rcgr = 0x9474, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_ff_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ff_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x9318, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src = { + .cmd_rcgr = 0x93ec, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_2, + .freq_tbl = ftbl_gpu_cc_hub_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hub_clk_src", + .parent_data = gpu_cc_parent_data_2, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_xo_clk_src = { + .cmd_rcgr = 0x9010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_3, + .freq_tbl = ftbl_gpu_cc_xo_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_xo_clk_src", + .parent_data = gpu_cc_parent_data_3, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_demet_div_clk_src = { + .reg = 0x9054, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gpu_cc_demet_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { + .reg = 0x9430, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gpu_cc_hub_ahb_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { + .reg = 0x942c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gpu_cc_hub_cx_int_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_xo_div_clk_src = { + .reg = 0x9050, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gpu_cc_xo_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x911c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x911c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x9120, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9120, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_apb_clk = { + .halt_reg = 0x912c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x912c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_apb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_ff_clk = { + .halt_reg = 0x914c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x914c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_ff_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x913c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x913c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x9130, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9130, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x9004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x9144, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9144, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_demet_clk = { + .halt_reg = 0x900c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x900c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_demet_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_demet_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk = { + .halt_reg = 0x9008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_freq_measure_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_xo_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_ff_clk = { + .halt_reg = 0x90c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x90c0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_ff_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk = { + .halt_reg = 0x90a8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x90a8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = { + .halt_reg = 0x90c8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x90c8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_rdvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk = { + .halt_reg = 0x90bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x90bc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_vsense_clk = { + .halt_reg = 0x90b0, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x90b0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_vsense_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x7000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk = { + .halt_reg = 0x93e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x93e8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hub_aon_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk = { + .halt_reg = 0x9148, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9148, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hub_cx_int_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk = { + .halt_reg = 0x9150, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9150, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_memnoc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { + .halt_reg = 0x9288, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9288, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_mnd1x_0_gfx3d_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = { + .halt_reg = 0x928c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x928c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_mnd1x_1_gfx3d_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x9134, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9134, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x9108, + .gds_hw_ctrl = 0x953c, + .clk_dis_wait_val = 8, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x905c, + .clamp_io_ctrl = 0x9504, + .resets = (unsigned int []){ GPUCC_GPU_CC_GX_BCR, + GPUCC_GPU_CC_ACD_BCR, + GPUCC_GPU_CC_GX_ACD_IROOT_BCR }, + .reset_count = 3, + .pd = { + .name = "gpu_gx_gdsc", + .power_on = gdsc_gx_do_nothing_enable, + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR, +}; + +static struct clk_regmap *gpu_cc_sm8450_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, + [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr, + [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr, + [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, + [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr, + [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, + [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, + [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, + [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr, + [GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr, +}; + +static const struct qcom_reset_map gpu_cc_sm8450_resets[] = { + [GPUCC_GPU_CC_XO_BCR] = { 0x9000 }, + [GPUCC_GPU_CC_GX_BCR] = { 0x9058 }, + [GPUCC_GPU_CC_CX_BCR] = { 0x9104 }, + [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 }, + [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 }, + [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, + [GPUCC_GPU_CC_FF_BCR] = { 0x9470 }, + [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 }, + [GPUCC_GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c }, +}; + +static struct gdsc *gpu_cc_sm8450_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_sm8450_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xa000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sm8450_desc = { + .config = &gpu_cc_sm8450_regmap_config, + .clks = gpu_cc_sm8450_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sm8450_clocks), + .resets = gpu_cc_sm8450_resets, + .num_resets = ARRAY_SIZE(gpu_cc_sm8450_resets), + .gdscs = gpu_cc_sm8450_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sm8450_gdscs), +}; + +static const struct of_device_id gpu_cc_sm8450_match_table[] = { + { .compatible = "qcom,sm8450-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm8450_match_table); + +static int gpu_cc_sm8450_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gpu_cc_sm8450_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + return qcom_cc_really_probe(pdev, &gpu_cc_sm8450_desc, regmap); +} + +static struct platform_driver gpu_cc_sm8450_driver = { + .probe = gpu_cc_sm8450_probe, + .driver = { + .name = "sm8450-gpucc", + .of_match_table = gpu_cc_sm8450_match_table, + }, +}; +module_platform_driver(gpu_cc_sm8450_driver); + +MODULE_DESCRIPTION("QTI GPU_CC SM8450 Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/gpucc-sm8550.c b/drivers/clk/qcom/gpucc-sm8550.c new file mode 100644 index 000000000000..8a2e3522af51 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm8550.c @@ -0,0 +1,611 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,sm8550-gpucc.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static const struct pll_vco lucid_ole_vco[] = { + { 249600000, 2300000000, 0 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config = { + /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */ + .l = 0x4444000d, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct alpha_pll_config gpu_cc_pll1_config = { + /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */ + .l = 0x44440016, + .alpha = 0xeaaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll gpu_cc_pll1 = { + .offset = 0x1000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_pll1", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .index = DT_GPLL0_OUT_MAIN }, + { .index = DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .index = DT_GPLL0_OUT_MAIN }, + { .index = DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .index = DT_GPLL0_OUT_MAIN }, + { .index = DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_3[] = { + { .index = DT_BI_TCXO }, +}; + +static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_ff_clk_src = { + .cmd_rcgr = 0x9474, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_ff_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_ff_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x9318, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src = { + .cmd_rcgr = 0x93ec, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_2, + .freq_tbl = ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_clk_src", + .parent_data = gpu_cc_parent_data_2, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_xo_clk_src = { + .cmd_rcgr = 0x9010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_3, + .freq_tbl = ftbl_gpu_cc_xo_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_xo_clk_src", + .parent_data = gpu_cc_parent_data_3, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_demet_div_clk_src = { + .reg = 0x9054, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_demet_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_xo_div_clk_src = { + .reg = 0x9050, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_xo_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x911c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x911c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x9120, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9120, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_crc_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_ff_clk = { + .halt_reg = 0x914c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x914c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cx_ff_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x913c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x913c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x9144, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9144, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_cxo_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk = { + .halt_reg = 0x9008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_freq_measure_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_xo_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x7000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk = { + .halt_reg = 0x93e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x93e8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_aon_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk = { + .halt_reg = 0x9148, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9148, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_cx_int_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk = { + .halt_reg = 0x9150, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9150, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_memnoc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { + .halt_reg = 0x9288, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9288, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_mnd1x_0_gfx3d_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = { + .halt_reg = 0x928c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x928c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_mnd1x_1_gfx3d_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x9134, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9134, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cc_cx_gdsc = { + .gdscr = 0x9108, + .gds_hw_ctrl = 0x953c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gpu_cc_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gpu_cc_gx_gdsc = { + .gdscr = 0x905c, + .clamp_io_ctrl = 0x9504, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gpu_cc_gx_gdsc", + .power_on = gdsc_gx_do_nothing_enable, + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *gpu_cc_sm8550_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr, + [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, + [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, + [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, + [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr, + [GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr, +}; + +static struct gdsc *gpu_cc_sm8550_gdscs[] = { + [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc, + [GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_sm8550_resets[] = { + [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 }, + [GPUCC_GPU_CC_CX_BCR] = { 0x9104 }, + [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, + [GPUCC_GPU_CC_FF_BCR] = { 0x9470 }, + [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 }, + [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 }, + [GPUCC_GPU_CC_GX_BCR] = { 0x9058 }, + [GPUCC_GPU_CC_XO_BCR] = { 0x9000 }, +}; + +static const struct regmap_config gpu_cc_sm8550_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9988, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sm8550_desc = { + .config = &gpu_cc_sm8550_regmap_config, + .clks = gpu_cc_sm8550_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sm8550_clocks), + .resets = gpu_cc_sm8550_resets, + .num_resets = ARRAY_SIZE(gpu_cc_sm8550_resets), + .gdscs = gpu_cc_sm8550_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sm8550_gdscs), +}; + +static const struct of_device_id gpu_cc_sm8550_match_table[] = { + { .compatible = "qcom,sm8550-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm8550_match_table); + +static int gpu_cc_sm8550_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gpu_cc_sm8550_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + /* + * Keep clocks always enabled: + * gpu_cc_cxo_aon_clk + * gpu_cc_demet_clk + */ + regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0)); + + return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap); +} + +static struct platform_driver gpu_cc_sm8550_driver = { + .probe = gpu_cc_sm8550_probe, + .driver = { + .name = "gpu_cc-sm8550", + .of_match_table = gpu_cc_sm8550_match_table, + }, +}; + +static int __init gpu_cc_sm8550_init(void) +{ + return platform_driver_register(&gpu_cc_sm8550_driver); +} +subsys_initcall(gpu_cc_sm8550_init); + +static void __exit gpu_cc_sm8550_exit(void) +{ + platform_driver_unregister(&gpu_cc_sm8550_driver); +} +module_exit(gpu_cc_sm8550_exit); + +MODULE_DESCRIPTION("QTI GPUCC SM8550 Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/lpasscc-sc8280xp.c b/drivers/clk/qcom/lpasscc-sc8280xp.c new file mode 100644 index 000000000000..43b37ce397cf --- /dev/null +++ b/drivers/clk/qcom/lpasscc-sc8280xp.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> + +#include "common.h" +#include "reset.h" + +static const struct qcom_reset_map lpass_audiocc_sc8280xp_resets[] = { + [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 }, + [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 }, + [LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xd8, 1 }, +}; + +static struct regmap_config lpass_audiocc_sc8280xp_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .name = "lpass-audio-csr", + .max_register = 0x1000, +}; + +static const struct qcom_cc_desc lpass_audiocc_sc8280xp_reset_desc = { + .config = &lpass_audiocc_sc8280xp_regmap_config, + .resets = lpass_audiocc_sc8280xp_resets, + .num_resets = ARRAY_SIZE(lpass_audiocc_sc8280xp_resets), +}; + +static const struct qcom_reset_map lpasscc_sc8280xp_resets[] = { + [LPASS_AUDIO_SWR_TX_CGCR] = { 0xc010, 1 }, +}; + +static struct regmap_config lpasscc_sc8280xp_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .name = "lpass-tcsr", + .max_register = 0x12000, +}; + +static const struct qcom_cc_desc lpasscc_sc8280xp_reset_desc = { + .config = &lpasscc_sc8280xp_regmap_config, + .resets = lpasscc_sc8280xp_resets, + .num_resets = ARRAY_SIZE(lpasscc_sc8280xp_resets), +}; + +static const struct of_device_id lpasscc_sc8280xp_match_table[] = { + { + .compatible = "qcom,sc8280xp-lpassaudiocc", + .data = &lpass_audiocc_sc8280xp_reset_desc, + }, { + .compatible = "qcom,sc8280xp-lpasscc", + .data = &lpasscc_sc8280xp_reset_desc, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpasscc_sc8280xp_match_table); + +static int lpasscc_sc8280xp_probe(struct platform_device *pdev) +{ + const struct qcom_cc_desc *desc = of_device_get_match_data(&pdev->dev); + + return qcom_cc_probe_by_index(pdev, 0, desc); +} + +static struct platform_driver lpasscc_sc8280xp_driver = { + .probe = lpasscc_sc8280xp_probe, + .driver = { + .name = "lpasscc-sc8280xp", + .of_match_table = lpasscc_sc8280xp_match_table, + }, +}; + +module_platform_driver(lpasscc_sc8280xp_driver); + +MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>"); +MODULE_DESCRIPTION("QTI LPASSCC SC8280XP Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c index 4273fce9a4a4..82f6bad144a9 100644 --- a/drivers/clk/qcom/mmcc-msm8974.c +++ b/drivers/clk/qcom/mmcc-msm8974.c @@ -485,7 +485,7 @@ static struct clk_rcg2 mdp_clk_src = { .name = "mdp_clk_src", .parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -2204,23 +2204,6 @@ static struct clk_branch ocmemcx_ocmemnoc_clk = { }, }; -static struct clk_branch oxili_ocmemgx_clk = { - .halt_reg = 0x402c, - .clkr = { - .enable_reg = 0x402c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "oxili_ocmemgx_clk", - .parent_data = (const struct clk_parent_data[]){ - { .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" }, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch ocmemnoc_clk = { .halt_reg = 0x50b4, .clkr = { @@ -2401,7 +2384,7 @@ static struct gdsc mdss_gdsc = { .pd = { .name = "mdss", }, - .pwrsts = PWRSTS_RET_ON, + .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc camss_jpeg_gdsc = { @@ -2512,7 +2495,6 @@ static struct clk_regmap *mmcc_msm8226_clocks[] = { [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr, [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr, [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr, - [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr, [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr, [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr, [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr, @@ -2670,7 +2652,6 @@ static struct clk_regmap *mmcc_msm8974_clocks[] = { [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr, [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr, [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr, - [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr, [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr, [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr, [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr, diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c new file mode 100644 index 000000000000..b148877fc73d --- /dev/null +++ b/drivers/clk/qcom/videocc-sm8350.c @@ -0,0 +1,552 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,sm8350-videocc.h> +#include <dt-bindings/reset/qcom,sm8350-videocc.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "reset.h" +#include "gdsc.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_BI_TCXO_AO, + P_SLEEP_CLK, + P_VIDEO_PLL0_OUT_MAIN, + P_VIDEO_PLL1_OUT_MAIN, +}; + +static const struct pll_vco lucid_5lpe_vco[] = { + { 249600000, 1750000000, 0 }, +}; + +static const struct alpha_pll_config video_pll0_config = { + .l = 0x25, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x2a9a699c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000000, + .test_ctl_hi1_val = 0x01800000, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll video_pll0 = { + .offset = 0x42c, + .vco_table = lucid_5lpe_vco, + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "video_pll0", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct alpha_pll_config video_pll1_config = { + .l = 0x2b, + .alpha = 0xc000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x2a9a699c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000000, + .test_ctl_hi1_val = 0x01800000, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll video_pll1 = { + .offset = 0x7d0, + .vco_table = lucid_5lpe_vco, + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "video_pll1", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] = { + { P_BI_TCXO_AO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0[] = { + { .index = DT_BI_TCXO_AO }, +}; + +static const struct parent_map video_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_VIDEO_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &video_pll0.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_VIDEO_PLL1_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &video_pll1.clkr.hw }, +}; + +static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_ahb_clk_src = { + .cmd_rcgr = 0xbd4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_0, + .freq_tbl = ftbl_video_cc_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_ahb_clk_src", + .parent_data = video_cc_parent_data_0, + .num_parents = ARRAY_SIZE(video_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { + F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src = { + .cmd_rcgr = 0xb94, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_1, + .freq_tbl = ftbl_video_cc_mvs0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_clk_src", + .parent_data = video_cc_parent_data_1, + .num_parents = ARRAY_SIZE(video_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = { + F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs1_clk_src = { + .cmd_rcgr = 0xbb4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_2, + .freq_tbl = ftbl_video_cc_mvs1_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_clk_src", + .parent_data = video_cc_parent_data_2, + .num_parents = ARRAY_SIZE(video_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_sleep_clk_src = { + .cmd_rcgr = 0xef0, + .mnd_width = 0, + .hid_width = 5, + .freq_tbl = ftbl_video_cc_sleep_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_sleep_clk_src", + .parent_data = &(const struct clk_parent_data){ + .index = DT_SLEEP_CLK, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 video_cc_xo_clk_src = { + .cmd_rcgr = 0xecc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_0, + .freq_tbl = ftbl_video_cc_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_xo_clk_src", + .parent_data = video_cc_parent_data_0, + .num_parents = ARRAY_SIZE(video_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0_div_clk_src = { + .reg = 0xd54, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = { + .reg = 0xc54, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0c_div2_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1_div_clk_src = { + .reg = 0xdd4, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = { + .reg = 0xcf4, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1c_div2_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_clk = { + .halt_reg = 0xd34, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xd34, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xd34, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_clk", + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk = { + .halt_reg = 0xc34, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc34, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0c_clk", + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_clk = { + .halt_reg = 0xdb4, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xdb4, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xdb4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_clk", + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_div2_clk = { + .halt_reg = 0xdf4, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xdf4, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xdf4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_div2_clk", + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs1c_div2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1c_clk = { + .halt_reg = 0xcd4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xcd4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1c_clk", + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs1c_div2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_sleep_clk = { + .halt_reg = 0xf10, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf10, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_sleep_clk", + .parent_hws = (const struct clk_hw*[]){ + &video_cc_sleep_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mvs0c_gdsc = { + .gdscr = 0xbf8, + .pd = { + .name = "mvs0c_gdsc", + }, + .flags = RETAIN_FF_ENABLE, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc mvs1c_gdsc = { + .gdscr = 0xc98, + .pd = { + .name = "mvs1c_gdsc", + }, + .flags = RETAIN_FF_ENABLE, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc mvs0_gdsc = { + .gdscr = 0xd18, + .pd = { + .name = "mvs0_gdsc", + }, + .flags = HW_CTRL | RETAIN_FF_ENABLE, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc mvs1_gdsc = { + .gdscr = 0xd98, + .pd = { + .name = "mvs1_gdsc", + }, + .flags = HW_CTRL | RETAIN_FF_ENABLE, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct clk_regmap *video_cc_sm8350_clocks[] = { + [VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr, + [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr, + [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr, + [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr, + [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr, + [VIDEO_CC_MVS1_DIV2_CLK] = &video_cc_mvs1_div2_clk.clkr, + [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr, + [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr, + [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr, + [VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr, + [VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr, + [VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr, + [VIDEO_PLL0] = &video_pll0.clkr, + [VIDEO_PLL1] = &video_pll1.clkr, +}; + +static const struct qcom_reset_map video_cc_sm8350_resets[] = { + [VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 }, + [VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 }, + [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 }, + [VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 }, + [VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 }, + [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 }, + [VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 }, +}; + +static struct gdsc *video_cc_sm8350_gdscs[] = { + [MVS0C_GDSC] = &mvs0c_gdsc, + [MVS1C_GDSC] = &mvs1c_gdsc, + [MVS0_GDSC] = &mvs0_gdsc, + [MVS1_GDSC] = &mvs1_gdsc, +}; + +static const struct regmap_config video_cc_sm8350_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10000, + .fast_io = true, +}; + +static struct qcom_cc_desc video_cc_sm8350_desc = { + .config = &video_cc_sm8350_regmap_config, + .clks = video_cc_sm8350_clocks, + .num_clks = ARRAY_SIZE(video_cc_sm8350_clocks), + .resets = video_cc_sm8350_resets, + .num_resets = ARRAY_SIZE(video_cc_sm8350_resets), + .gdscs = video_cc_sm8350_gdscs, + .num_gdscs = ARRAY_SIZE(video_cc_sm8350_gdscs), +}; + +static int video_cc_sm8350_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + regmap = qcom_cc_map(pdev, &video_cc_sm8350_desc); + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); + return PTR_ERR(regmap); + } + + clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); + clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); + + /* + * Keep clocks always enabled: + * video_cc_ahb_clk + * video_cc_xo_clk + */ + regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); + + ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; +} + +static const struct of_device_id video_cc_sm8350_match_table[] = { + { .compatible = "qcom,sm8350-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_sm8350_match_table); + +static struct platform_driver video_cc_sm8350_driver = { + .probe = video_cc_sm8350_probe, + .driver = { + .name = "sm8350-videocc", + .of_match_table = video_cc_sm8350_match_table, + }, +}; +module_platform_driver(video_cc_sm8350_driver); + +MODULE_DESCRIPTION("QTI SM8350 VIDEOCC Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c new file mode 100644 index 000000000000..7d0029b8b799 --- /dev/null +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -0,0 +1,463 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,sm8450-videocc.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, +}; + +enum { + P_BI_TCXO, + P_VIDEO_CC_PLL0_OUT_MAIN, + P_VIDEO_CC_PLL1_OUT_MAIN, +}; + +static const struct pll_vco lucid_evo_vco[] = { + { 249600000, 2020000000, 0 }, +}; + +static const struct alpha_pll_config video_cc_pll0_config = { + /* .l includes CAL_L_VAL, L_VAL fields */ + .l = 0x0044001e, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, +}; + +static struct clk_alpha_pll video_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct alpha_pll_config video_cc_pll1_config = { + /* .l includes CAL_L_VAL, L_VAL fields */ + .l = 0x0044002b, + .alpha = 0xc000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, +}; + +static struct clk_alpha_pll video_cc_pll1 = { + .offset = 0x1000, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_pll1", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &video_cc_pll0.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL1_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &video_cc_pll1.clkr.hw }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { + F(576000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src = { + .cmd_rcgr = 0x8000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_0, + .freq_tbl = ftbl_video_cc_mvs0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_clk_src", + .parent_data = video_cc_parent_data_0, + .num_parents = ARRAY_SIZE(video_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = { + F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs1_clk_src = { + .cmd_rcgr = 0x8018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_1, + .freq_tbl = ftbl_video_cc_mvs1_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_clk_src", + .parent_data = video_cc_parent_data_1, + .num_parents = ARRAY_SIZE(video_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0_div_clk_src = { + .reg = 0x80b8, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = { + .reg = 0x806c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0c_div2_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1_div_clk_src = { + .reg = 0x80dc, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = { + .reg = 0x8094, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1c_div2_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_clk = { + .halt_reg = 0x80b0, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x80b0, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x80b0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk = { + .halt_reg = 0x8064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8064, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0c_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_clk = { + .halt_reg = 0x80d4, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x80d4, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x80d4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1c_clk = { + .halt_reg = 0x808c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x808c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1c_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs1c_div2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc video_cc_mvs0c_gdsc = { + .gdscr = 0x804c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, + .pd = { + .name = "video_cc_mvs0c_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0_gdsc = { + .gdscr = 0x809c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, + .pd = { + .name = "video_cc_mvs0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &video_cc_mvs0c_gdsc.pd, + .flags = RETAIN_FF_ENABLE | HW_CTRL, +}; + +static struct gdsc video_cc_mvs1c_gdsc = { + .gdscr = 0x8074, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, + .pd = { + .name = "video_cc_mvs1c_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs1_gdsc = { + .gdscr = 0x80c0, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, + .pd = { + .name = "video_cc_mvs1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &video_cc_mvs1c_gdsc.pd, + .flags = RETAIN_FF_ENABLE | HW_CTRL, +}; + +static struct clk_regmap *video_cc_sm8450_clocks[] = { + [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr, + [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr, + [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr, + [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr, + [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr, + [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr, + [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr, + [VIDEO_CC_PLL0] = &video_cc_pll0.clkr, + [VIDEO_CC_PLL1] = &video_cc_pll1.clkr, +}; + +static struct gdsc *video_cc_sm8450_gdscs[] = { + [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc, + [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc, + [VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc, + [VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc, +}; + +static const struct qcom_reset_map video_cc_sm8450_resets[] = { + [CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80e0 }, + [CVP_VIDEO_CC_MVS0_BCR] = { 0x8098 }, + [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 }, + [CVP_VIDEO_CC_MVS1_BCR] = { 0x80bc }, + [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8070 }, + [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 }, + [VIDEO_CC_MVS1C_CLK_ARES] = { 0x808c, 2 }, +}; + +static const struct regmap_config video_cc_sm8450_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9f4c, + .fast_io = true, +}; + +static struct qcom_cc_desc video_cc_sm8450_desc = { + .config = &video_cc_sm8450_regmap_config, + .clks = video_cc_sm8450_clocks, + .num_clks = ARRAY_SIZE(video_cc_sm8450_clocks), + .resets = video_cc_sm8450_resets, + .num_resets = ARRAY_SIZE(video_cc_sm8450_resets), + .gdscs = video_cc_sm8450_gdscs, + .num_gdscs = ARRAY_SIZE(video_cc_sm8450_gdscs), +}; + +static const struct of_device_id video_cc_sm8450_match_table[] = { + { .compatible = "qcom,sm8450-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_sm8450_match_table); + +static int video_cc_sm8450_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + regmap = qcom_cc_map(pdev, &video_cc_sm8450_desc); + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); + return PTR_ERR(regmap); + } + + clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); + clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); + + /* + * Keep clocks always enabled: + * video_cc_ahb_clk + * video_cc_sleep_clk + * video_cc_xo_clk + */ + regmap_update_bits(regmap, 0x80e4, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x8130, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x8114, BIT(0), BIT(0)); + + ret = qcom_cc_really_probe(pdev, &video_cc_sm8450_desc, regmap); + + pm_runtime_put(&pdev->dev); + + return ret; +} + +static struct platform_driver video_cc_sm8450_driver = { + .probe = video_cc_sm8450_probe, + .driver = { + .name = "video_cc-sm8450", + .of_match_table = video_cc_sm8450_match_table, + }, +}; + +static int __init video_cc_sm8450_init(void) +{ + return platform_driver_register(&video_cc_sm8450_driver); +} +subsys_initcall(video_cc_sm8450_init); + +static void __exit video_cc_sm8450_exit(void) +{ + platform_driver_unregister(&video_cc_sm8450_driver); +} +module_exit(video_cc_sm8450_exit); + +MODULE_DESCRIPTION("QTI VIDEOCC SM8450 Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c new file mode 100644 index 000000000000..e2400fe23e60 --- /dev/null +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -0,0 +1,470 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,sm8450-videocc.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, +}; + +enum { + P_BI_TCXO, + P_VIDEO_CC_PLL0_OUT_MAIN, + P_VIDEO_CC_PLL1_OUT_MAIN, +}; + +static const struct pll_vco lucid_ole_vco[] = { + { 249600000, 2300000000, 0 }, +}; + +static const struct alpha_pll_config video_cc_pll0_config = { + /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */ + .l = 0x44440025, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll video_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct alpha_pll_config video_cc_pll1_config = { + /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */ + .l = 0x44440036, + .alpha = 0xb000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll video_cc_pll1 = { + .offset = 0x1000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_pll1", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &video_cc_pll0.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL1_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &video_cc_pll1.clkr.hw }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { + F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src = { + .cmd_rcgr = 0x8000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_0, + .freq_tbl = ftbl_video_cc_mvs0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_clk_src", + .parent_data = video_cc_parent_data_0, + .num_parents = ARRAY_SIZE(video_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = { + F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs1_clk_src = { + .cmd_rcgr = 0x8018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_1, + .freq_tbl = ftbl_video_cc_mvs1_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_clk_src", + .parent_data = video_cc_parent_data_1, + .num_parents = ARRAY_SIZE(video_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0_div_clk_src = { + .reg = 0x80c4, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = { + .reg = 0x8070, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0c_div2_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1_div_clk_src = { + .reg = 0x80ec, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = { + .reg = 0x809c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1c_div2_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_clk = { + .halt_reg = 0x80b8, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x80b8, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x80b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk = { + .halt_reg = 0x8064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8064, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0c_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_clk = { + .halt_reg = 0x80e0, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x80e0, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x80e0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1c_clk = { + .halt_reg = 0x8090, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8090, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1c_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_mvs1c_div2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc video_cc_mvs0c_gdsc = { + .gdscr = 0x804c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, + .pd = { + .name = "video_cc_mvs0c_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0_gdsc = { + .gdscr = 0x80a4, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, + .pd = { + .name = "video_cc_mvs0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &video_cc_mvs0c_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL, +}; + +static struct gdsc video_cc_mvs1c_gdsc = { + .gdscr = 0x8078, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, + .pd = { + .name = "video_cc_mvs1c_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs1_gdsc = { + .gdscr = 0x80cc, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, + .pd = { + .name = "video_cc_mvs1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &video_cc_mvs1c_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL, +}; + +static struct clk_regmap *video_cc_sm8550_clocks[] = { + [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr, + [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr, + [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr, + [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr, + [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr, + [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr, + [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr, + [VIDEO_CC_PLL0] = &video_cc_pll0.clkr, + [VIDEO_CC_PLL1] = &video_cc_pll1.clkr, +}; + +static struct gdsc *video_cc_sm8550_gdscs[] = { + [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc, + [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc, + [VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc, + [VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc, +}; + +static const struct qcom_reset_map video_cc_sm8550_resets[] = { + [CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 }, + [CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 }, + [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 }, + [CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 }, + [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 }, + [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 }, + [VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 }, +}; + +static const struct regmap_config video_cc_sm8550_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9f4c, + .fast_io = true, +}; + +static struct qcom_cc_desc video_cc_sm8550_desc = { + .config = &video_cc_sm8550_regmap_config, + .clks = video_cc_sm8550_clocks, + .num_clks = ARRAY_SIZE(video_cc_sm8550_clocks), + .resets = video_cc_sm8550_resets, + .num_resets = ARRAY_SIZE(video_cc_sm8550_resets), + .gdscs = video_cc_sm8550_gdscs, + .num_gdscs = ARRAY_SIZE(video_cc_sm8550_gdscs), +}; + +static const struct of_device_id video_cc_sm8550_match_table[] = { + { .compatible = "qcom,sm8550-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table); + +static int video_cc_sm8550_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + regmap = qcom_cc_map(pdev, &video_cc_sm8550_desc); + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); + return PTR_ERR(regmap); + } + + clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); + clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); + + /* + * Keep clocks always enabled: + * video_cc_ahb_clk + * video_cc_sleep_clk + * video_cc_xo_clk + */ + regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0)); + + ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap); + + pm_runtime_put(&pdev->dev); + + return ret; +} + +static struct platform_driver video_cc_sm8550_driver = { + .probe = video_cc_sm8550_probe, + .driver = { + .name = "video_cc-sm8550", + .of_match_table = video_cc_sm8550_match_table, + }, +}; + +static int __init video_cc_sm8550_init(void) +{ + return platform_driver_register(&video_cc_sm8550_driver); +} +subsys_initcall(video_cc_sm8550_init); + +static void __exit video_cc_sm8550_exit(void) +{ + platform_driver_unregister(&video_cc_sm8550_driver); +} +module_exit(video_cc_sm8550_exit); + +MODULE_DESCRIPTION("QTI VIDEOCC SM8550 Driver"); +MODULE_LICENSE("GPL"); |