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authorMichael Turquette <mturquette@baylibre.com>2016-07-15 19:13:36 -0700
committerMichael Turquette <mturquette@baylibre.com>2016-07-15 19:15:12 -0700
commitca1d2e269f593b318a75f3ffb9befc1ec8b6f2fd (patch)
tree555daf5390d4f71e13faa433eb94544dd2811312 /drivers/clk
parente16fb2e6355c1c1b41623af9e01ada196e2af098 (diff)
downloadlwn-ca1d2e269f593b318a75f3ffb9befc1ec8b6f2fd.tar.gz
lwn-ca1d2e269f593b318a75f3ffb9befc1ec8b6f2fd.zip
Revert "clk: gxbb: expose CLKID_MMC_PCLK"
This reverts commit e16fb2e6355c1c1b41623af9e01ada196e2af098. Updated documentation from the chip vendor reveals that this clock is not required for correct operation of the MMC controller. As such, do not expose it to DT. Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/meson/gxbb.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 8355ecd27b81..a2adf3448b59 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -234,7 +234,7 @@
#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
-/* CLKID_MMC_PCLK */
+#define CLKID_MMC_PCLK 66
#define CLKID_DVIN 67
#define CLKID_UART2 68
#define CLKID_SANA 69