diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2024-10-01 11:50:16 +0100 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2024-11-02 19:19:47 +0800 |
| commit | e0f253a52ccee3cf3eb987e99756e20c68a1aac9 (patch) | |
| tree | a4c5a3580d61f63c6047025c4f6b402a76ce2e8e /drivers/clk | |
| parent | c7e09a613bbddd0eea086e475855aba3b2410148 (diff) | |
| download | lwn-e0f253a52ccee3cf3eb987e99756e20c68a1aac9.tar.gz lwn-e0f253a52ccee3cf3eb987e99756e20c68a1aac9.zip | |
clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset
To work around a limitation in our clock modelling, we try to force two
bits in the AUDIO0 PLL to 0, in the CCU probe routine.
However the ~ operator only applies to the first expression, and does
not cover the second bit, so we end up clearing only bit 1.
Group the bit-ORing with parentheses, to make it both clearer to read
and actually correct.
Fixes: 35b97bb94111 ("clk: sunxi-ng: Add support for the D1 SoC clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20241001105016.1068558-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun20i-d1.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c index 9633d4506891..c80ac2dfbb60 100644 --- a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c +++ b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c @@ -1371,7 +1371,7 @@ static int sun20i_d1_ccu_probe(struct platform_device *pdev) /* Enforce m1 = 0, m0 = 0 for PLL_AUDIO0 */ val = readl(reg + SUN20I_D1_PLL_AUDIO0_REG); - val &= ~BIT(1) | BIT(0); + val &= ~(BIT(1) | BIT(0)); writel(val, reg + SUN20I_D1_PLL_AUDIO0_REG); /* Force fanout-27M factor N to 0. */ |