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| author | Abel Vesa <abel.vesa@linaro.org> | 2024-05-30 17:05:24 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-07-08 11:40:17 -0500 |
| commit | 14539c88972bd984f1f04c9e601c1a2835d3e5d2 (patch) | |
| tree | 5782e3474a15b3cd97f9433784a5e7d2971e9e04 /drivers/clk | |
| parent | 9db4585eca22fcd0422a94ac792f87dcbf74b643 (diff) | |
| download | lwn-14539c88972bd984f1f04c9e601c1a2835d3e5d2.tar.gz lwn-14539c88972bd984f1f04c9e601c1a2835d3e5d2.zip | |
clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks
Allow the USB3 second and third GCC PHY pipe clocks to propagate the
rate to the pipe clocks provided by the QMP combo PHYs. The first
instance is already doing that.
Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240530-x1e80100-clk-gcc-usb3-sec-tert-set-parent-rate-v1-1-7b2b04cad545@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/gcc-x1e80100.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c index fc80011342da..6ffb3ddcae08 100644 --- a/drivers/clk/qcom/gcc-x1e80100.c +++ b/drivers/clk/qcom/gcc-x1e80100.c @@ -5269,6 +5269,7 @@ static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -5339,6 +5340,7 @@ static struct clk_branch gcc_usb3_tert_phy_pipe_clk = { &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw, }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, |