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| author | Philipp Zabel <p.zabel@pengutronix.de> | 2015-11-30 22:07:53 +0100 |
|---|---|---|
| committer | Philipp Zabel <p.zabel@pengutronix.de> | 2016-05-06 17:47:40 +0200 |
| commit | 4585945bf1d348d006f7270beea3dae09fee3413 (patch) | |
| tree | b41934ae0bb5a4f9c615f86808abdb5cc2365b01 /drivers/clk | |
| parent | 06445994fece2ae458419fbadc1b2107336615d6 (diff) | |
| download | lwn-4585945bf1d348d006f7270beea3dae09fee3413.tar.gz lwn-4585945bf1d348d006f7270beea3dae09fee3413.zip | |
clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output
The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8173.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 85c0bfc626ae..cf4fcb61ed28 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -1095,6 +1095,11 @@ static void __init mtk_apmixedsys_init(struct device_node *node) clk_data->clks[cku->id] = clk; } + clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0, + base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO, + NULL); + clk_data->clks[CLK_APMIXED_HDMI_REF] = clk; + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", |