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| author | Tero Kristo <t-kristo@ti.com> | 2017-02-09 11:24:37 +0200 |
|---|---|---|
| committer | Tero Kristo <t-kristo@ti.com> | 2017-03-08 13:06:15 +0200 |
| commit | 6c0afb503937a12a8d20a805fcf263e31afa9871 (patch) | |
| tree | 4e0d29a53aae87a587dc802be0697facf90703e8 /drivers/clk/ti/clkt_dpll.c | |
| parent | 473adbf4e02857a6b78dfb3d9fcf752638bbadb9 (diff) | |
| download | lwn-6c0afb503937a12a8d20a805fcf263e31afa9871.tar.gz lwn-6c0afb503937a12a8d20a805fcf263e31afa9871.zip | |
clk: ti: convert to use proper register definition for all accesses
Currently, TI clock driver uses an encapsulated struct that is cast into
a void pointer to store all register addresses. This can be considered
as rather nasty hackery, and prevents from expanding the register
address field also. Instead, replace all the code to use proper struct
in place for this, which contains all the previously used data.
This patch is rather large as it is touching multiple files, but this
can't be split up as we need to avoid any boot breakage.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'drivers/clk/ti/clkt_dpll.c')
| -rw-r--r-- | drivers/clk/ti/clkt_dpll.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/ti/clkt_dpll.c b/drivers/clk/ti/clkt_dpll.c index b919fdfe8256..ce98da2c10be 100644 --- a/drivers/clk/ti/clkt_dpll.c +++ b/drivers/clk/ti/clkt_dpll.c @@ -213,7 +213,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) if (!dd) return -EINVAL; - v = ti_clk_ll_ops->clk_readl(dd->control_reg); + v = ti_clk_ll_ops->clk_readl(&dd->control_reg); v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); @@ -249,14 +249,14 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) return 0; /* Return bypass rate if DPLL is bypassed */ - v = ti_clk_ll_ops->clk_readl(dd->control_reg); + v = ti_clk_ll_ops->clk_readl(&dd->control_reg); v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); if (_omap2_dpll_is_in_bypass(v)) return clk_hw_get_rate(dd->clk_bypass); - v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg); + v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); dpll_mult = v & dd->mult_mask; dpll_mult >>= __ffs(dd->mult_mask); dpll_div = v & dd->div1_mask; |