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| author | Icenowy Zheng <icenowy@aosc.io> | 2017-09-10 20:40:06 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-09-17 12:03:08 +0200 |
| commit | 70641ccad7d19b8229bf1cac33f5b8e03fdc7c5a (patch) | |
| tree | 0077ec3c16bb9a68b6a1c4837384e0b54ae6ffe1 /drivers/clk/sunxi-ng | |
| parent | 62d212bdb022deeb875f92f6e376c799e3f35eca (diff) | |
| download | lwn-70641ccad7d19b8229bf1cac33f5b8e03fdc7c5a.tar.gz lwn-70641ccad7d19b8229bf1cac33f5b8e03fdc7c5a.zip | |
clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock
The GPU clock on H3 has only one parent, PLL-GPU, and the PLL is only
the parent of the GPU clock. The GPU clock can be tweaked by tweaking
the PLL-GPU clock.
Add CLK_SET_RATE_PARENT flag to allow tweaking the GPU clock via
tweaking PLL-CPU.
Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index 7a81c4885836..543c46d0e045 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c @@ -484,7 +484,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", - 0x1a0, 0, 3, BIT(31), 0); + 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); static struct ccu_common *sun8i_h3_ccu_clks[] = { &pll_cpux_clk.common, |