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| author | Xingyu Wu <xingyu.wu@starfivetech.com> | 2023-07-17 10:30:37 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-07-19 18:08:00 +0100 |
| commit | 616bc1dea1ac8909dfcd6d32802df6fe50eddde8 (patch) | |
| tree | d39b3b35a2179eb315f5597b563f31e13d34d252 /drivers/clk/starfive/Makefile | |
| parent | a097a5ec14dff59568b1e6c8bd8cc37a21d8811f (diff) | |
| download | lwn-616bc1dea1ac8909dfcd6d32802df6fe50eddde8.tar.gz lwn-616bc1dea1ac8909dfcd6d32802df6fe50eddde8.zip | |
clk: starfive: Add StarFive JH7110 PLL clock driver
Add driver for the StarFive JH7110 PLL clock controller
and they work by reading and setting syscon registers.
Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'drivers/clk/starfive/Makefile')
| -rw-r--r-- | drivers/clk/starfive/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index f3df7d957b1e..b48e539e52b0 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -4,5 +4,6 @@ obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o +obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL) += clk-starfive-jh7110-pll.o obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o |