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| author | Sunyeal Hong <sunyeal.hong@samsung.com> | 2024-08-22 08:26:51 +0900 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-08-23 09:21:28 +0200 |
| commit | 9224e288f2e1f9161cf0c54122ac9168b6b68877 (patch) | |
| tree | 621e0b6ab1695a3825adb075fad4c0dead8d1040 /drivers/clk/samsung/clk-pll.h | |
| parent | c0979bc8845068b542ef65086f3173494e6a6faf (diff) | |
| download | lwn-9224e288f2e1f9161cf0c54122ac9168b6b68877.tar.gz lwn-9224e288f2e1f9161cf0c54122ac9168b6b68877.zip | |
clk: samsung: clk-pll: Add support for pll_531x
pll531x PLL is used in Exynos Auto v920 SoC for shared pll.
pll531x: Integer/fractional PLL with mid frequency FVCO (800 to 3120 MHz)
PLL531x
FOUT = (MDIV x FIN)/(PDIV x 2^SDIV) for integer PLL
FOUT = (MDIV + F/2^32-F[31]) x FIN/(PDIV x 2^SDIV) for fractional PLL
Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20240821232652.1077701-4-sunyeal.hong@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'drivers/clk/samsung/clk-pll.h')
| -rw-r--r-- | drivers/clk/samsung/clk-pll.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 1efbe4c446d0..3481941ba07a 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -42,6 +42,7 @@ enum samsung_pll_type { pll_0516x, pll_0517x, pll_0518x, + pll_531x, }; #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ |