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| author | Xing Zheng <zhengxing@rock-chips.com> | 2016-03-09 10:43:31 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-03-27 00:53:20 +0100 |
| commit | 9387bfd19b457085189d918ef117ffd63c4d67a0 (patch) | |
| tree | e56d741224bf5eecb58f4c748f57b987c9be5117 /drivers/clk/rockchip/clk.h | |
| parent | f55532a0c0b8bb6148f4e07853b876ef73bc69ca (diff) | |
| download | lwn-9387bfd19b457085189d918ef117ffd63c4d67a0.tar.gz lwn-9387bfd19b457085189d918ef117ffd63c4d67a0.zip | |
clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type
Because there are some frac clock mux nodes don't have a gate node on
the RK3399.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk.h')
| -rw-r--r-- | drivers/clk/rockchip/clk.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 39c198bbcbee..f3da205073ee 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -428,6 +428,22 @@ struct rockchip_clk_branch { .child = ch, \ } +#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \ + { \ + .id = _id, \ + .branch_type = branch_fraction_divider, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .flags = f, \ + .muxdiv_offset = mo, \ + .div_shift = 16, \ + .div_width = 16, \ + .div_flags = df, \ + .gate_offset = -1, \ + .child = ch, \ + } + #define MUX(_id, cname, pnames, f, o, s, w, mf) \ { \ .id = _id, \ |