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| author | Xing Zheng <zhengxing@rock-chips.com> | 2016-03-28 17:51:37 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-03-28 14:57:07 +0200 |
| commit | 115510053e5e5872f1f19a2220b04aab5542c5c4 (patch) | |
| tree | 4ab3c6c8522d91cd2b04313a5dcd9a200cee11a3 /drivers/clk/rockchip/clk.h | |
| parent | 485a40d7cd4aab5ae939320278809776388f5c06 (diff) | |
| download | lwn-115510053e5e5872f1f19a2220b04aab5542c5c4.tar.gz lwn-115510053e5e5872f1f19a2220b04aab5542c5c4.zip | |
clk: rockchip: add clock controller for the RK3399
Add the clock tree definition for the new RK3399 SoC.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk.h')
| -rw-r--r-- | drivers/clk/rockchip/clk.h | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index cb6a63963693..880349f6d3d7 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -34,7 +34,7 @@ struct clk; #define HIWORD_UPDATE(val, mask, shift) \ ((val) << (shift) | (mask) << ((shift) + 16)) -/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */ +/* register positions shared by RK2928, RK3036, RK3066, RK3188, RK3228, RK3399 */ #define RK2928_PLL_CON(x) ((x) * 0x4) #define RK2928_MODE_CON 0x40 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) @@ -93,6 +93,26 @@ struct clk; #define RK3368_EMMC_CON0 0x418 #define RK3368_EMMC_CON1 0x41c +#define RK3399_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300) +#define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400) +#define RK3399_GLB_SRST_FST 0x500 +#define RK3399_GLB_SRST_SND 0x504 +#define RK3399_GLB_CNT_TH 0x508 +#define RK3399_MISC_CON 0x50c +#define RK3399_RST_CON 0x510 +#define RK3399_RST_ST 0x514 +#define RK3399_SDMMC_CON0 0x580 +#define RK3399_SDMMC_CON1 0x584 +#define RK3399_SDIO_CON0 0x588 +#define RK3399_SDIO_CON1 0x58c + +#define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80) +#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100) +#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110) + enum rockchip_pll_type { pll_rk3036, pll_rk3066, |