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| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2023-05-02 19:06:17 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-05-08 09:14:33 +0200 |
| commit | 7f91fe3a71aa43700eac2650e3b01d50cbbb6f48 (patch) | |
| tree | 33e157e3b3db8f5cb318930c78b126bcc46b05e7 /drivers/clk/renesas | |
| parent | ac9a78681b921877518763ba0e89202254349d1b (diff) | |
| download | lwn-7f91fe3a71aa43700eac2650e3b01d50cbbb6f48.tar.gz lwn-7f91fe3a71aa43700eac2650e3b01d50cbbb6f48.zip | |
clk: renesas: r8a779a0: Add PWM clock
Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20230502170618.55967-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a779a0-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index fcc8279647a6..4c2872f45387 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -170,6 +170,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { DEF_MOD("msi3", 621, R8A779A0_CLK_MSO), DEF_MOD("msi4", 622, R8A779A0_CLK_MSO), DEF_MOD("msi5", 623, R8A779A0_CLK_MSO), + DEF_MOD("pwm0", 628, R8A779A0_CLK_S1D8), DEF_MOD("rpc-if", 629, R8A779A0_CLK_RPCD2), DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8), DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8), |